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| Intel(R) PXA270 Processor Electrical, Mechanical, and Thermal Specification Data Sheet High-performance processor: -- Intel XScale(R) microarchitecture with Intel(R) Wireless MMXTM Technology -- 7 Stage pipeline -- 32 KB instruction cache -- 32 KB data cache -- 2 KB "mini" data cache -- Extensive data buffering 256 Kbytes of internal SRAM for high speed code or data storage preserved during low-power states High-speed baseband processor interface (Mobile Scalable Link) Rich serial peripheral set: -- AC'97 audio port -- I2S audio port -- USB Client controller -- USB Host controller -- USB On-The-Go controller -- Three high-speed UARTs (two with hardware flow control) -- FIR and SIR infrared communications port Hardware debug features -- IEEE JTAG interface with boundary scan Hardware performance-monitoring features with on-chip trace buffer Real-time clock Operating-system timers LCD Controller Universal Subscriber Identity Module interface Low power: -- Wireless Intel Speedstep(R) Technology -- Less than 500 mW typical internal dissipation -- Supply voltage may be reduced to 0.85 V -- Four low-power modes -- Dynamic voltage and frequency management High-performance memory controller: -- Four banks of SDRAM: up to 104 MHz @ 2.5V, 3.0V, and 3.3V I/O interface -- Six static chip selects -- Support for PCMCIA and Compact Flash -- Companion chip interface Flexible clocking: -- CPU clock from 104 to 624 MHz -- Flexible memory clock ratios -- Frequency changes -- Functional clock gating Additional peripherals for system connectivity: -- SD Card / MMC Controller (with SPI mode support) -- Memory Stick card controller -- Three SSP controllers -- Two I2C controllers -- Four pulse-width modulators (PWMs) -- Keypad interface with both direct and matrix keys support -- Most peripheral pins double as GPIOs Order Number 280002-005 www..com INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PXA270 processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. 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Copyright (c) Intel Corporation, 2005. All Rights Reserved. ii Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Contents Contents 1 Introduction .........................................................................................................1-1 1.1 About This Document .................................................................................1-1 1.1.1 Number Representation ................................................................1-1 1.1.2 Typographical Conventions...........................................................1-1 1.1.3 Applicable Documents...................................................................1-2 2 3 Functional Overview ...........................................................................................2-1 Package Information ...........................................................................................3-1 3.1 3.2 3.3 3.4 3.5 Package Information ..................................................................................3-1 Processor Materials....................................................................................3-6 Junction To Case Temperature Thermal Resistance .................................3-7 Processor Markings....................................................................................3-7 Tray Drawing ..............................................................................................3-8 Ball Map View.............................................................................................4-2 4.1.1 13x13 mm VF-BGA Ball map ........................................................4-2 4.1.2 23x23 mm PBGA Ball map............................................................4-6 Pin Use.......................................................................................................4-9 Signal Types.............................................................................................4-27 Memory Controller Reset and Initialization...............................................4-28 Power-Supply Pins ...................................................................................4-29 Absolute Maximum Ratings........................................................................5-1 Operating Conditions..................................................................................5-1 5.2.1 Internal Power Domains ................................................................5-6 Power-Consumption Specifications............................................................5-6 DC Specification.........................................................................................5-8 Oscillator Electrical Specifications..............................................................5-9 5.5.1 32.768-kHz Oscillator Specifications .............................................5-9 5.5.2 13.000-MHz Oscillator Specifications..........................................5-11 CLK_PIO and CLK_TOUT Specifications ................................................5-12 48 MHz Output Specifications ..................................................................5-13 AC Test Load Specifications ......................................................................6-1 Reset and Power Manager Timing Specifications......................................6-2 6.2.1 Power-On Timing Specifications ...................................................6-2 6.2.2 Hardware Reset Timing.................................................................6-4 6.2.3 Watchdog Reset Timing ................................................................6-5 6.2.4 GPIO Reset Timing .......................................................................6-5 6.2.5 Sleep Mode Timing .......................................................................6-6 6.2.6 Deep-Sleep Mode Timing..............................................................6-7 4 Pin Listing and Signal Definitions .....................................................................4-1 4.1 4.2 4.3 4.4 4.5 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6 6.1 6.2 Electrical Specifications .....................................................................................5-1 AC Timing Specifications...................................................................................6-1 Electrical, Mechanical, and Thermal Specification iii Intel(R) PXA270 Processor Contents 6.3 6.4 6.5 6.6 6.7 6.2.7 Standby-Mode Timing .................................................................6-10 6.2.8 Idle-Mode Timing.........................................................................6-10 6.2.9 Frequency-Change Timing..........................................................6-10 6.2.10 Voltage-Change Timing...............................................................6-11 GPIO Timing Specifications .....................................................................6-11 Memory and Expansion-Card Timing Specifications................................6-12 6.4.1 Internal SRAM Read/Write Timing Specifications .......................6-12 6.4.2 SDRAM Parameters and Timing Diagrams.................................6-12 6.4.3 ROM Parameters and Timing Diagrams .....................................6-18 6.4.4 Flash Memory Parameters and Timing Diagrams.......................6-23 6.4.5 SRAM Parameters and Timing Diagrams ...................................6-33 6.4.6 Variable-Latency I/O Parameters and Timing Diagrams.............6-36 6.4.7 Expansion-Card Interface Parameters and Timing Diagrams.....6-40 LCD Timing Specifications .......................................................................6-43 SSP Timing Specifications .......................................................................6-44 JTAG Boundary Scan Timing Specifications............................................6-45 Figures 2-1 Intel(R) PXA270 Processor Block Diagram, Typical System................................2-2 3-1 13x13mm VF-BGA Intel(R) PXA270 Processor Package, top view .....................3-1 3-2 13x13mm VF-BGA Intel(R) PXA270 Processor Package, bottom view ...............3-2 3-3 13x13mm VF-BGA Intel(R) PXA270 Processor Package, side view ...................3-3 3-4 VF-BGA Product Information Decoder...............................................................3-3 3-5 23x23 mm PBGA Intel(R) PXA270 Processor Package (Top View) ....................3-4 3-6 23x23 mm PBGA Intel(R) PXA270 Processor Package (Bottom View) ...............3-4 3-7 23x23 mm PBGA Intel(R) PXA270 Processor Package (Side View) ...................3-5 3-8 PBGA Product Information Decoder ..................................................................3-5 3-9 13x13mm VF-BGA Intel(R) PXA270 Processor Package, bottom view ...............3-6 3-10Intel(R) PXA270 Processor Production Markings, (Laser Mark on Top Side)......3-7 4-1 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) .............................4-2 4-2 13x13 mm VF-BGA Ball Map, Top View (upper right quarter) ...........................4-3 4-3 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) ...........................4-4 4-4 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) ........................4-5 4-5 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter) ..............................4-6 4-6 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter)............................4-7 4-7 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) ..............................4-8 4-8 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)............................4-9 6-1 AC Test Load .....................................................................................................6-2 6-2 Power On Reset Timing .....................................................................................6-3 6-3 Hardware Reset Timing .....................................................................................6-4 6-4 GPIO Reset Timing ............................................................................................6-5 6-5 Sleep Mode Timing ............................................................................................6-7 6-6 Deep-Sleep-Mode Timing ..................................................................................6-8 6-7 SDRAM Timing ................................................................................................6-15 6-8 SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing............................6-16 6-9 SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing ...............6-17 6-10SDRAM Fly-by DMA Timing.............................................................................6-18 6-1132-Bit Non-burst ROM, SRAM, or Flash Read Timing .....................................6-20 iv Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Contents 6-12 32-Bit Burst-of-Eight ROM or Flash Read Timing ............................................6-21 6-13 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing..........6-22 6-14 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing ....................................6-23 6-15 Synchronous Flash Burst-of-Eight Read Timing ..............................................6-26 6-16 Synchronous Flash Stacked Burst-of-Eight Read Timing ................................6-27 6-17 First-Access Latency Configuration Timing......................................................6-28 6-18 Synchronous Flash Burst Read Example.........................................................6-30 6-19 32-Bit Flash Write Timing .................................................................................6-31 6-20 32-Bit Stacked Flash Write Timing ...................................................................6-32 6-21 16-Bit Flash Write Timing .................................................................................6-33 6-22 32-Bit SRAM Write Timing ...............................................................................6-35 6-23 16-bit SRAM Write for 4/2/1 Byte(s) Timing .....................................................6-36 6-24 32-Bit VLIO Read Timing .................................................................................6-38 6-25 32-Bit VLIO Write Timing..................................................................................6-39 6-26 Expansion-Card Memory or I/O 16-Bit Access Timing.....................................6-41 6-27 Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ............6-42 6-28 LCD Timing Definitions.....................................................................................6-43 6-29 SSP Master Mode Timing Definitions...............................................................6-44 6-30 Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral .........................................................................................................6-44 6-31 Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral .........................................................................................................6-45 6-32 JTAG Boundary-Scan Timing...........................................................................6-46 Tables 1-1 Supplemental Documentation ............................................................................1-2 3-1 Processor Material Properties ............................................................................3-7 4-1 Pin Use Summary ............................................................................................4-10 4-2 Pin Use and Mapping Notes.............................................................................4-27 4-3 Signal Types.....................................................................................................4-28 4-4 Memory Controller Pin Reset Values ...............................................................4-28 4-5 Discrete (13x13 VF-BGA) Power Supply Pin Summary...................................4-29 5-1 Absolute Maximum Ratings................................................................................5-1 5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2 5-3 Memory Voltage and Frequency Electrical Specifications .................................5-4 5-4 Core Voltage and Frequency Electrical Specifications.......................................5-4 5-5 Internally Generated Power Domain Descriptions .............................................5-6 5-6 Core Voltage Specifications For Lower Power Modes .......................................5-6 5-7 Power-Consumption Specifications....................................................................5-7 5-8 Standard Input, Output, and I/O Pin DC Operating Conditions ..........................5-8 5-9 Typical 32.768-kHz Crystal Requirements .........................................................5-9 5-10 Typical External 32.768-kHz Oscillator Requirements ....................................5-11 5-11 Typical 13.000-MHz Crystal Requirements......................................................5-11 5-12 Typical External 13.000-MHz Oscillator Requirements....................................5-12 5-13 CLK_PIO Specifications ...................................................................................5-12 5-14 CLK_TOUT Specifications ...............................................................................5-12 5-15 48 MHz Output Specifications ..........................................................................5-13 6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions ..........................6-1 6-2 Power-On Timing Specifications(OSCC[CRI] = 0) .............................................6-3 6-3 Hardware Reset Timing Specifications (OSCC[CRI] = 0) ..................................6-4 Electrical, Mechanical, and Thermal Specification v Intel(R) PXA270 Processor Contents 6-4 Hardware Reset Timing Specifications (OSCC[CRI] = 1) .................................6-5 6-5 GPIO Reset Timing Specifications .....................................................................6-6 6-6 Sleep-Mode Timing Specifications .....................................................................6-7 6-7 Deep-Sleep Mode Timing Specifications ...........................................................6-8 6-8 GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode .................................6-9 6-9 Standby-Mode Timing Specifications ...............................................................6-10 6-10Idle-Mode Timing Specifications ......................................................................6-10 6-11Frequency-Change Timing Specifications .......................................................6-10 6-12Voltage-Change Timing Specification for a 1-Byte Command.........................6-11 6-13GPIO Timing Specifications .............................................................................6-11 6-14SRAM Read/Write AC Specification ................................................................6-12 6-15SDRAM Interface AC Specifications ................................................................6-13 6-16ROM AC Specification .....................................................................................6-18 6-17Synchronous Flash Read AC Specifications....................................................6-24 6-18Flash Memory AC Specification .......................................................................6-30 6-19SRAM Write AC Specification ..........................................................................6-34 6-20VLIO Timing .....................................................................................................6-37 6-21Expansion-Card Interface AC Specifications ...................................................6-40 6-22LCD Timing Specifications ...............................................................................6-43 6-23SSP Master Mode Timing Specifications .........................................................6-44 6-24Timing Specification SSP Slave Mode Transmitting Data to External Peripheral .........................................................................................................6-45 6-25Timing Specification for SSP Slave Mode Receiving Data from External Peripheral .........................................................................................................6-45 6-26Boundary Scan Timing Specifications..............................................................6-45 vi Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Contents Revision History Date April 2004 June 2004 June 2004 Revision -001 -002 -003 Description First public release of the EMTS Added 23x23 mm 360-ball PBGA package Added 624-MHz active and idle power consumption values to Table 5-7. Modified Power Consumption introduction in Chapter 5, "PowerConsumption Specifications" October 2004 -004 Modified Watchdog Reset timing description Chapter 6, "Reset and Power Manager Timing Specifications" Corrected 13 MHz Oscillator slew rate specification Section 5.5, "Oscillator Electrical Specifications" Added note to VCC_BB voltage specifications, Chapter 5, "Electrical Specifications" April 2005 -005 Modified Core Voltage and Frequency Electrial Specifications, Chapter 5, "Electrical Specifications" Modified SDRAM Parameters and Timing Diagrams, Chapter 6, "AC Timing Specifications" Modified Processor Material Properties,Chapter 3, "Package Information" Electrical, Mechanical, and Thermal Specification vii Intel(R) PXA270 Processor Contents viii Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Contents Documentation Feedback Form for the Intel(R) PXA270 Processor Electrical, Mechanical, Thermal Specification Your input allows us to create documentation that better meets your needs. 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Any other comments about the quality, accuracy, usability of this document: ___________________________________________________________________________ _______________________________________________________________________________ Electrical, Mechanical, and Thermal Specification ix Intel(R) PXA270 Processor Contents x Electrical, Mechanical, and Thermal Specification Introduction 1 The Intel(R) PXA270 processor (PXA270 processor) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances in mobile technology over its predecessor, the Intel(R) PXA255 processor. These same attributes and features also make the PXA270 processor ideal for embedded applications. The PXA270 processor redefines scalability by operating from 104 MHz up to 624 MHz, providing enough performance for the most demanding mobile applications. The PXA270 processor is the first Intel processor to include Intel(R) Wireless MMXTM technology, enabling high-performance, low-power multimedia acceleration with a general-purpose instruction set. Intel(R) Quick Capture technology provides a flexible and powerful camera interface for capturing digital images and video. While performance is key in the PXA270 processor, power consumption is also a critical component. The new capabilities of Wireless Intel SpeedStep(R) technology set the standard for low-power consumption. The PXA270 processor is offered in two packages: 13x13 mm VFBGA and 23x23 mm PBGA. 1.1 About This Document This document constitutes the electrical, mechanical, and thermal specifications for the PXA270 processor. It contains a functional overview, mechanical data, package signal locations, targeted electrical specifications, and functional bus waveforms. For detailed functional descriptions other than parametric performance, refer to the Intel(R) PXA27x Processor Family Developers Manual. 1.1.1 Number Representation All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is represented as 0x6B in hexadecimal and 0b110_1011 in binary. 1.1.2 Typographical Conventions All signal and register-bit names appear in uppercase. Active low items are prefixed with a lowercase "n". Bits within a signal name are enclosed in angle brackets: EXTERNAL_ADDRESS<31:0> nCS<1> Bits within a register bit field are enclosed in square brackets: REGISTER_BITFIELD[3:0] REGISTER_BIT[0] Electrical, Mechanical, and Thermal Specification 1-1 Intel(R) PXA270 Processor Introduction Single-bit items have either of two states: * clear -- the item contains the value 0b0. To clear a bit, write 0b0 to it. * set -- the item contains the value 0b1. To set a bit, write 0b1 to it. 1.1.3 Applicable Documents Table 1-1 lists supplemental information sources for the PXA270 processor. Contact an Intel representative for the latest document revisions and ordering instructions. Table 1-1. Supplemental Documentation Document Title Intel(R) PXA27x Processor Family Developers Manual ARM(R) Architecture Version 5T Specification (Document number ARM* DDI 0100D-10), and ARM (R) Architecture Reference Manual (Document number ARM* DDI 0100B) Intel(R) XScaleTM Core Developer's Manual Intel(R) Wireless MMXTM Technology Developer's Guide Intel(R) PXA27x Processor Design Guide Intel(R) PXA27x Processor Power Supply Requirements Application Note 1-2 Electrical, Mechanical, and Thermal Specification Functional Overview 2 The Intel(R) PXA270 processor is an integrated system-on-a-chip microprocessor for high performance, dynamic, low-power portable handheld and hand-set devices as well as embedded platforms. It incorporates the Intel XScale(R) technology which complies with the ARM* version 5TE instruction set (excluding floating-point instructions) and follows the ARM* programmer's model. The PXA270 processor also provides Intel(R) Wireless MMXTM media enhancement technology, which supports integer instructions to accelerate audio and video processing. In addition, it incorporates Wireless Intel Speedstep(R) Technology, which provides sophisticated power management capabilities enabling excellent MIPs/mW performance. The PXA270 processor provides a scalable, bi-directional data interface to a cellular baseband processor, supporting seven logical channels and other features. The operating-system (OS) timer channels and synchronous serial ports (SSPs) also accept an external network clock input so that they can be synchronized to the cellular network. The processor also provides a Universal Subscriber Identity Module* (USIM) card interface. The PXA270 processor memory interface gives designers flexibility as it supports a variety of external memory types. The processor also provides four 64 kilobyte banks of on-chip SRAM, which can be used for program code or multimedia data. Each bank can be configured independently to retain its contents when the processor enters a low-power mode. An integrated LCD panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit color pixels. A 256-byte palette RAM provides flexible color mapping. A set of serial devices and general-system resources offers computational and connectivity capability for a variety of applications. Figure 2-1 shows the block diagram for a typical PXA270 processor system. Electrical, Mechanical, and Thermal Specification 2-1 Intel(R) PXA270 Processor Functional Overview Figure 2-1. Intel(R) PXA270 Processor Block Diagram, Typical System LCD LCD RTC RTC OS Timers OS Tim ers Address nd Data us Ad dre ss aandDa ta BBus 44xx PWM PWM Interrupt Interrupt Controller C ontroller 33xxSSP SSP USIM USIM I2S I2S Peripheral Bus Peripheral Bus AC97 AC97 Internal LCD Camera Internal LCD Controller SRAM Interface SRAM Controller Memory Memory Controller Controller Address Addr ess and and Data Data Variable Var iable Latency I/O Latency I/O Control Control General Purpose /O General Pur pose I I/O ASIC ASIC Socket 0 Socket 0 Full Function Full Function UART UA RT Bluetooth Bluet oot h* UART U AR T IrDA IrD A I22 C DMA DMA Controller Controller And and Bridge Bri dge Intel(R) Wireless MMXTM Int el(R) Wireless MMXTM System Bus System Bus PCMCIA & CF PCMCIA & CF Control Control XCVR Socket 1 XCVR Socket 1 IC USB USB Client C lie nt BB Processor BB Proce ss or Interface Inter face Keypad K eypad Interface Interfa ce SDCard/MMC S DC ard/M MC Interface Inte r face Memory Stick Mem ory Stick Interface Int er face USB USB OTG OTG Camera Interface MicroMicroarchitecture architectur e Debug Debug Controller Controller 13 13 MHz MHz Osc Osc Intel(R) Intel(R) (R) XScaleTM XScaleTM USB USB Host Host Dynamic Dynamic Memory Memor y Control Control Static Static Memory Memory Control Control SDRAM/ SDRAM Boot ROM Power Management Power Management Clock Control Clock Cont rol 32.768 32.768 kHz kHz Osc Osc ROM/ ROM/ Flash/ Flash/ SRAM SRAM PrimaryyGPIO Primar GPIO JTAG JTAG 2-2 Electrical, Mechanical, and Thermal Specification Package Information This chapter provides the mechanical specifications for the PXA270 processor. 3 The PXA270 processor is offered in two packages. The 13- by 13-mm, 356-ball, 0.50-mm VFBGA molded matrix array package is shown in Figure 3-1, Figure 3-2, and Figure 3-3. The 23- by 23-mm, 360-ball, 1.0-mm PBGA molded matrix array package is shown in Figure 3-5, Figure 3-6, and Figure 3-7. 3.1 Package Information Figure 3-1. 13x13mm VF-BGA Intel(R) PXA270 Processor Package, top view A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD Electrical, Mechanical, and Thermal Specification 3-1 Intel(R) PXA270 Processor Package Information Note: Figure 3-2 and Figure 3-3 show all dimensions in millimeters (mm). Figure 3-2. 13x13mm VF-BGA Intel(R) PXA270 Processor Package, bottom view 0.15 M C 0.15 M C A B o0.300.05 (356) 130.10 11.50 0.50 0.50 A B 11.50 130.10 3-2 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Package Information Figure 3-3. 13x13mm VF-BGA Intel(R) PXA270 Processor Package, side view 0.450.05 0.10 C 0.210.04 0.18 MIN. - 0.30 MAX. C Figure 3-4. VF-BGA Product Information Decoder R C P X A 2 7 0 C 0 C 4 1 6 Package Type RC=Leaded RT=Lead-Free Intel XScale(R) Family 270=Discrete product Product Family Member Commercial Temperature rating Stepping Electrical, Mechanical, and Thermal Specification 0.91 MIN. - 1.0 MAX. Speed 312 MHz 416 MHz 520 MHz 624 MHz SEATING PLANE 0.12 C 3-3 Intel(R) PXA270 Processor Package Information Note: Figure 3-5, Figure 3-6 and Figure 3-7 show all dimensions in millimeters (mm). Figure 3-5. 23x23 mm PBGA Intel(R) PXA270 Processor Package (Top View) A1 CORNER 14.70 0.25 Figure 3-6. 23x23 mm PBGA Intel(R) PXA270 Processor Package (Bottom View) 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB PIN #1 CORNER 1.00 1.00 1.00 1.00 3-4 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Package Information Figure 3-7. 23x23 mm PBGA Intel(R) PXA270 Processor Package (Side View) // 3 0.15 C 0.20 C SEATING PLANE Figure 3-8. PBGA Product Information Decoder F W P X A 2 7 0 C 1 C 4 1 6 Package Type FW = Leaded NH = Lead-Free Speed 312 MHz 416 MHz 520 MHz Temperature Rating C = -25 to 85 C E = -40 to 85 C Intel XScale(R) Family Product Family Member 270 = Discrete product Stepping Electrical, Mechanical, and Thermal Specification 3-5 Intel(R) PXA270 Processor Package Information 3.2 Processor Materials Figure 3-9. 13x13mm VF-BGA Intel(R) PXA270 Processor Package, bottom view Table 3-1 describes the basic material properties of the processor components. 3-6 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Package Information Table 3-1. Processor Material Properties Component Mold compound Solder balls(Leaded) Solder balls(Pb-free) VF-BGA Material ShinEtsu KMC 2500 VAT1 63% Sn/37% Pb 94.5% Sn / 5.0% Ag / 0.5% Cu PBGA Material Sumitomo G770LE 63% Sn/37% Pb 94.5% Sn / 5.0% Ag / 0.5% Cu 3.3 Junction To Case Temperature Thermal Resistance Parameter Theta Jc VF-BGA Value and Units 2 degrees C / watt PBGA Value and Units 1.4 degrees C / watt 3.4 Processor Markings The diagram in this section details the processor's top markings, which identify the PXA270 processor in the 356-ball VF-BGA and 360-ball PBGA package. Refer to Figure 3-4 for product information. A Pb-Free (lead-free) package is indicated by the letter "E" on the 3rd line of information (Intel legal line). The "E" appears after the date stamp. Figure 3-10. Intel(R) PXA270 Processor Production Markings, (Laser Mark on Top Side) g Laser Mark on top side of Package i PXA270C0C416 FPO# M C `03 Product Lot # Intel Legal TAIWAN COO PIN 1 INDICATOR Electrical, Mechanical, and Thermal Specification 3-7 Intel(R) PXA270 Processor Package Information 3.5 Tray Drawing For tray drawing information, refer to the Intel Developer website for the Intel(R) Wireless Communications and Computing Package Users Guide. 3-8 Electrical, Mechanical, and Thermal Specification Pin Listing and Signal Definitions This chapter describes the signals and pins for the Intel(R) PXA270 processor. 4 For descriptions of all PXA270 processor signals, refer to the "System Architecture" chapter in the Intel(R) PXA27x Processor Family Developer's Manual. Table 4-2 lists the mapping of signals to specific package pins. Many of the package pins are multiplexed so that they can be configured for use as a general-purpose I/O signal or as one of two or three alternate functions using the GPIO alternate-function select registers. Some signals can be configured to appear on one of several different package pins. Electrical, Mechanical, and Thermal Specification 4-1 Intel(R) PXA270 Processor Pin Listing and Signal Definitions 4.1 Note: Ball Map View In the following ball map figures the lowercase letter "n", which normally indicates negation, appears as uppercase "N". 4.1.1 13x13 mm VF-BGA Ball map Figure 4-1 through Figure 4-4 shows the ball map for the VF-BGA PXA270 processor. Figure 4-1. 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) 1 2 3 4 5 6 7 8 9 10 11 12 A VSS_CORE VSS_CORE GPIO<15> VCC_MEM VCC_SRAM MA<1> VCC_CORE VCC_SRAM VCC_SRAM GPIO<49> GPIO<47> VCC_IO B VSS_CORE VSS_CORE NCS<0> VCC_SRAM VSS_CORE GPIO<33> GPIO<78> VCC_MEM GPIO<18> GPIO<12> GPIO<46> VCC_CORE C MA<18> MA<22> VCC_MEM MA<24> VSS_MEM MA<0> GPIO<80> GPIO<79> RDNWR GPIO<13> GPIO<11> GPIO<31> D MA<17> MA<21> VCC_CORE MA<23> VSS_MEM MA<25> VSS_CORE VSS_CORE VSS_MEM VSS_CORE VSS_IO VSS_CORE E MA<13> VCC_MEM MA<19> MA<20> F VCC_MEM MA<14> MA<16> VSS_MEM G MA<8> MA<11> MA<12> MA<15> H VCC_MEM MA<9> MA<10> VSS_MEM J MA<3> MA<6> MA<7> VSS_MEM K MD<15> MA<4> MA<5> MA<2> VSS_CORE VSS_CORE VSS_CORE L MD<14> MD<31> VCC_MEM VSS_MEM VSS_CORE VSS_CORE VSS_CORE M VCC_MEM MD<30> MD<29> MD<13> VSS_CORE VSS_CORE VSS_CORE 4-2 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Figure 4-2. 13x13 mm VF-BGA Ball Map, Top View (upper right quarter) 13 14 15 16 17 18 19 20 21 22 23 24 GPIO<113> GPIO<28> GPIO<37> VCC_IO GPIO<24> GPIO<16> GPIO<92> GPIO<32> GPIO<34> GPIO<118> VCC_USB VCC_USB A GPIO<29> GPIO<38> GPIO<26> GPIO<23> GPIO<110> GPIO<112> GPIO<35> GPIO<44> VCC_CORE USBC_P VCC_USB VCC_USB B GPIO<30> GPIO<36> GPIO<27> GPIO<17> GPIO<111> GPIO<41> GPIO<45> USBC_N GPIO<42> GPIO<43> GPIO<88> GPIO<116> C GPIO<22> GPIO<40> VSS_IO GPIO<25> GPIO<109> VSS_IO GPIO<39> GPIO<117> VSS_CORE GPIO<89> USBH_N<1> GPIO<114> D GPIO<115> USBH_P<1> UIO VCC_USIM E VSS_IO GPIO<90> GPIO<91> VCC_CORE F VSS_CORE GPIO<59> GPIO<60> GPIO<58> G VSS_IO GPIO<62> GPIO<63> GPIO<61> H VSS_CORE GPIO<64> VCC_CORE VCC_LCD J VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<66> GPIO<67> GPIO<65> K VSS_CORE VSS_CORE VSS_CORE GPIO<68> GPIO<71> GPIO<69> VCC_CORE L VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<73> VCC_CORE GPIO<70> M Electrical, Mechanical, and Thermal Specification 4-3 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Figure 4-3. 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) N MD<27> MD<28> MD<12> VSS_MEM VSS_CORE VSS_CORE VSS_CORE P VCC_MEM MD<11> MD<26> MD<10> VSS_CORE VSS_CORE VSS_CORE R MD<24> VSS_MEM MD<25> MD<9> VSS_CORE VSS_CORE VSS_CORE T MD<23> VCC_CORE MD<8> VSS_MEM U MD<7> VCC_MEM VSS_CORE MD<5> V MD<21> MD<22> MD<6> VSS_MEM W MD<20> VCC_MEM VCC_CORE VSS_CORE Y MD<19> MD<4> MD<3> VSS_MEM AA MD<18> VCC_MEM MD<2> MD<16> VSS_MEM NSDCAS VSS_CORE VSS_MEM VSS_MEM GPIO<55> GPIO<84> VSS_CORE AB MD<1> VSS_MEM MD<17> MD<0> NWE GPIO<20> NSDCS<0> NSDCS<1> DQM<0> DQM<1> GPIO<56> GPIO<81> AC VCC_MEM VCC_MEM VSS_MEM SDCLK<0> NOE VCC_MEM NSDRAS VCC_MEM DQM<2> DQM<3> GPIO<57> GPIO<85> AD VCC_MEM VCC_MEM SDCLK<2> VCC_CORE GPIO<21> SDCKE SDCLK<1> VCC_MEM GPIO<82> GPIO<83> VCC_CORE VCC_BB 1 2 3 4 5 6 7 8 9 10 11 12 4-4 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Figure 4-4. 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) VSS_CORE VSS_CORE VSS_CORE VSS_IO GPIO<86> GPIO<87> GPIO<72> N VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<76> GPIO<75> VCC_LCD P VSS_CORE VSS_CORE VSS_CORE GPIO<77> GPIO<19> GPIO<74> VCC_CORE R TMS TCK TESTCLK GPIO<14> T NTRST GPIO<9> TDI VSS_IO U VSS GPIO<0> GPIO<10> TDO V GPIO<3> NVDD_FAUL T GPIO<4> CLK_REQ W NRESET_O UT NRESET PWR_EN GPIO<1> Y VSS_BB GPIO<54> VSS_CORE VSS_IO GPIO<97> GPIO<95> VSS_IO PWR_CAP< 3> VSS TXTAL_IN TXTAL_OUT SYS_EN AA GPIO<50> GPIO<53> GPIO<106> GPIO<105> GPIO<102> GPIO<99> GPIO<93> VCC_BATT PWR_CAP< PWR_OUT 0> BOOT_SEL NBATT_FAU LT AB GPIO<48> GPIO<52> GPIO<107> GPIO<103> GPIO<101> GPIO<100> GPIO<96> VCC_PLL PXTAL_IN PWR_CAP< 2> VSS VSS AC GPIO<51> GPIO<108> GPIO<104> VCC_CORE VCC_IO GPIO<98> GPIO<94> VSS_PLL PXTAL_OUT PWR_CAP< 1> VSS VSS AD 13 14 15 16 17 18 19 20 21 22 23 24 Electrical, Mechanical, and Thermal Specification 4-5 Intel(R) PXA270 Processor Pin Listing and Signal Definitions 4.1.2 23x23 mm PBGA Ball map Figure 4-5. 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter) 1 2 3 4 5 6 7 8 9 10 11 A VSS_MEM VSS_MEM MA[25] GPIO[15] GPIO[79] GPIO[13] GPIO[12] GPIO[11] GPIO[46] GPIO[113] GPIO[29] B VSS_MEM VCC_MEM VSS_MEM VCC_RAM MA[1] VSS_MEM VCC_RAM VCC_RAM VSS_MEM VCC_IO GPIO[30] C MA[16] MA[17] VCC_MEM MA[24] VCC_RAM VCC_MEM GPIO[33] RDNWR VCC_MEM GPIO[47] GPIO[31] D MA[14] MA[15] MA[19] MA[22] MA[0] NCS_0 GPIO[80] GPIO[78] GPIO[18] GPIO[49] VCC_CORE E MA[11] MA[12] MA[21] MA[23] VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE F MA[9] VSS_MEM VCC_MEM MA[20] VCC_CORE G MA[7] MA[8] MA[13] MA[18] VSS_CORE H MA[4] VSS_MEM VCC_MEM MA[10] VCC_CORE J MA[3] MA[2] MA[6] MA[5] VSS_CORE VSS_CORE VSS_CORE VSS_CORE K MD[15] MD[30] VCC_MEM MD[31] VSS_CORE VSS_CORE VSS_CORE L MD[14] VSS_MEM MD[29] VCC_CORE VSS_CORE VSS_CORE VSS_CORE 4-6 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Figure 4-6. 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter) 12 13 14 15 16 17 18 19 20 21 22 GPIO[22] GPIO[38] GPIO[26] GPIO[25] GPIO[23] GPIO[111] GPIO[92] GPIO[41] GPIO[44] VCC_USB VCC_USB A VSS_IO GPIO[36] GPIO[24] VSS_IO GPIO[112] GPIO[39] VSS_IO GPIO[34] GPIO[118] GPIO[43] VCC_USB B GPIO[40] GPIO[27] GPIO[16] GPIO[110] GPIO[32] GPIO[45] GPIO[117] NC NC GPIO[89] GPIO[88] C GPIO[28] GPIO[37] VCC_IO GPIO[17] GPIO[109] GPIO[35] USBC_P VCC_USB GPIO[42] VSS_IO USBH_N[1] D VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE USBC_N GPIO[116] GPIO[115] USBH_P[1] E VCC_CORE GPIO[114] UIO VCC_USIM GPIO[61] F VSS_CORE GPIO[91] GPIO[58] GPIO[60] GPIO[62] G VCC_CORE GPIO[90] GPIO[59] VSS_IO GPIO[64] H VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO[66] GPIO[63] VCC_LCD GPIO[69] J VSS_CORE VSS_CORE VSS_CORE GPIO[67] GPIO[65] GPIO[68] GPIO[70] K VSS_CORE VSS_CORE VSS_CORE VCC_CORE GPIO[71] GPIO[72] GPIO[73] L Electrical, Mechanical, and Thermal Specification 4-7 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Figure 4-7. 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) M MD[13] MD[11] VCC_MEM MD[12] VSS_CORE VSS_CORE VSS_CORE N MD[28] MD[26] MD[24] MD[25] VSS_CORE VSS_CORE VSS_CORE P MD[27] VSS_MEM VCC_MEM MD[8] VSS_CORE VSS_CORE VSS_CORE VSS_CORE R MD[10] MD[23] MD[21] MD[7] VCC_CORE T MD[9] VSS_MEM VCC_MEM MD[5] VSS_CORE U MD[22] MD[6] MD[4] MD[2] VCC_CORE V MD[20] VSS_MEM VCC_MEM MD[16] VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE W MD[19] MD[18] MD[1] MD[0] GPIO[20] NSDRAS SDCKE DQM[0] GPIO[55] GPIO[81] VCC_CORE Y MD[3] MD[17] VCC_MEM NSDCAS VCC_MEM GPIO[21] VCC_MEM NSDCS[1] VCC_MEM GPIO[84] GPIO[48] AA VSS_MEM VCC_MEM NWE NOE NSDCS[0] VSS_MEM DQM[1] GPIO[82] VSS_MEM GPIO[85] VCC_BB AB VSS_MEM VSS_MEM SDCLK[0] SDCLK[2] SDCLK[1] DQM[2] DQM[3] GPIO[56] GPIO[57] GPIO[83] VSS_BB 1 2 3 4 5 6 7 8 9 10 11 4-8 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Figure 4-8. 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter) VSS_CORE VSS_CORE VSS_CORE VCC_LCD GPIO[86] VSS_IO GPIO[87] M VSS_CORE VSS_CORE VSS_CORE VSS_IO GPIO[75] GPIO[76] GPIO[74] N VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO[19] GPIO[14] GPIO[77] TESTCLK P VCC_CORE TCK TMS TDO TDI R VSS_CORE GPIO[4] NTRST CLK_REQ GPIO[9] T VCC_CORE NBATT_FAU LT GPIO[0] GPIO[1] GPIO[10] U VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE BOOT_SEL NVDD_FAUL T SYS_EN GPIO[3] V GPIO[50] GPIO[106] GPIO[104] VCC_IO GPIO[96] PWR_CAP [3] VSS PWR_OUT NRESET NRESET_O UT PWR_EN W GPIO[52] GPIO[105] GPIO[102] GPIO[97] GPIO[93] VCC_BATT PWR_CAP [2] PWR_CAP [0] VSS TXTAL_IN TXTAL_OUT Y GPIO[53] GPIO[108] VSS_IO GPIO[100] GPIO[98] GPIO[94] VSS_IO VSS_PLL PXTAL_OUT PWR_CAP [1] VSS AA GPIO[51] GPIO[54] GPIO[107] GPIO[103] GPIO[101] GPIO[99] GPIO[95] VCC_PLL PXTAL_IN VSS VSS AB 12 13 14 15 16 17 18 19 20 21 22 4.2 Pin Use The pin-use summary shown in Table 4-1 does not include the 36 center balls identified as K10 through R15 (VF-BGA) or J9 through P14 (PBGA), all of which function as VSS_CORE (see the recommendations for connecting the 36 center balls in the Intel(R) PXA27x Processor Family Design Guide). Each signal's alternate function inputs are shown in the upper section of each signal row and the outputs are shown in the lower section of each signal row. For example, GPIO<48> has a primary input function of CIF_DD<5> and a secondary output function of nPOE. Electrical, Mechanical, and Thermal Specification 4-9 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 1 of 17) VF-BGA Ball# (13x13) VCC_MEM D6 C4 D4 C2 D2 E4 E3 C1 D1 F3 G4 F2 E1 G3 G2 H3 H2 G1 J3 J2 K3 K2 J1 K4 A6 C6 L2 M2 M3 N2 A3 C4 E4 D4 E3 F4 D3 G4 C2 C1 D2 D1 G3 E2 E1 H4 F1 G2 G1 J3 J4 H1 J1 J2 B5 D5 K4 K2 L3 N1 MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0> MD<31> MD<30> MD<29> MD<28> OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ ICOC Z ICOC Z ICOC Z ICOC Z MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0> MD<31> MD<30> MD<29> MD<28> MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0> MD<31> MD<30> MD<29> MD<28> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 PBGA Ball# (23x23) Name Type Function After Reset Primary Function Secondary Alternate Function Third Alternate Function Reset State Sleep State NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-10 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 2 of 17) VF-BGA Ball# (13x13) N1 P3 R3 R1 T1 V2 V1 W1 Y1 AA1 AB3 AA4 K1 L1 M4 N3 P2 P4 R4 T3 U1 V3 PBGA Ball# (23x23) P1 N2 N4 N3 R2 U1 R3 V1 W1 W2 Y2 V4 K1 L1 M1 M4 M2 R1 T1 P4 R4 U2 Name Type ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Function After Reset MD<27> MD<26> MD<25> MD<24> MD<23> MD<22> MD<21> MD<20> MD<19> MD<18> MD<17> MD<16> MD<15> MD<14> MD<13> MD<12> MD<11> MD<10> MD<9> MD<8> MD<7> MD<6> Primary Function MD<27> MD<26> MD<25> MD<24> MD<23> MD<22> MD<21> MD<20> MD<19> MD<18> MD<17> MD<16> MD<15> MD<14> MD<13> MD<12> MD<11> MD<10> MD<9> MD<8> MD<7> MD<6> Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Sleep State MD<27> MD<26> MD<25> MD<24> MD<23> MD<22> MD<21> MD<20> MD<19> MD<18> MD<17> MD<16> MD<15> MD<14> MD<13> MD<12> MD<11> MD<10> MD<9> MD<8> MD<7> MD<6> Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-11 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 3 of 17) VF-BGA Ball# (13x13) U4 Y2 Y3 AA3 AB1 AB4 AC5 AB5 AC7 AA6 AB9 AB10 AC9 AC10 AB7 AB8 AD6 AC4 AD7 AD3 C9 B3 PBGA Ball# (23x23) T4 U3 Y1 U4 W3 W4 AA4 AA3 W6 Y4 W8 AA7 AB6 AB7 AA5 Y8 W7 AB3 AB5 AB4 C8 D6 Name Type ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OCZ OC OC OC OCZ OC OCZ OCZ ICOC Z Function After Reset MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> nOE nWE nSDRAS nSDCAS DQM<0> DQM<1> DQM<2> DQM<3> nSDCS<0> nSDCS<1> SDCKE SDCLK<0> SDCLK<1> SDCLK<2> RDnWR nCS<0> Primary Function MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> nOE nWE nSDRAS nSDCAS DQM<0> DQM<1> DQM<2> DQM<3> nSDCS<0> nSDCS<1> SDCKE SDCLK<0> SDCLK<1> SDCLK<2> RDnWR nCS<0> -- Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nCS<1> Refer to Table 4-4 -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Sleep State MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> NOE NWE NSDRAS NSDCAS DQM<0> DQM<1> DQM<2> DQM<3> NSDCS< 0> NSDCS< 1> SDCKE SDCLK<0 > SDCLK<1 > SDCLK<2 > RDNWR NCS<0> GPIO<15 > Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Refer to Table 4-4 Pu-1 Note[1] A3 A4 GPIO<15> nPCE<1> RDY -- Note[4] B9 D9 GPIO<18 > ICOC Z GPIO<18> Pd-0 Note[1] Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-12 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 4 of 17) VF-BGA Ball# (13x13) PBGA Ball# (23x23) Name Type Function After Reset Primary Function DREQ<0> AB6 W5 GPIO<20 > ICOC Z GPIO<20> nSDCS<2> Refer to Table 4-4 -- AD5 Y6 GPIO<21 > ICOC Z GPIO<21> nSDCS<3> Refer to Table 4-4 FFRXD19 B6 C7 GPIO<33 > ICOC Z GPIO<33> DVAL<1> -- A10 D10 GPIO<49 > ICOC Z GPIO<49> -- -- B7 D8 GPIO<78 > ICOC Z GPIO<78> nPCE<2> -- C8 A5 GPIO<79 > ICOC Z GPIO<79> PSKTSEL DREQ<1> C7 D7 GPIO<80 > ICOC Z GPIO<80> -- DVAL<0> FFDSR19 nCS<5> Refer to Table 4-4 -- nPWE Refer to Table 4-4 -- nCS<2> Refer to Table 4-4 -- nCS<3> Refer to Table 4-4 MBREQ nCS<4> Refer to Table 4-4 -- -- PWM_OUT <2> -- PWM_OUT <3> Pu-1 Note[1] Note[4] Pu-1 Note[1] Note[4] -- -- Pu-1 Note[1] Note[4] MBGNT -- Pu-1 Note[1] Note [5] MBGNT -- Pu-1 Note[1] Note [4] -- -- -- -- Pu-1 Note[1] Note[3] Secondary Alternate Function MBREQ Third Alternate Function -- Reset State Sleep State Pu-1 Note[1] Note[3] VCC_BB CIF_DD<5> AC13 Y11 GPIO<48 > ICOC Z GPIO<48> BB_OB_DAT<1 > CIF_DD<3> AB13 W12 GPIO<50 > ICOC Z GPIO<50> BB_OB_DAT<2 > CIF_DD<2> AD13 AB12 GPIO<51 > ICOC Z GPIO<51> BB_OB_DAT<3 > -- nPOE Refer to Table 4-4 -- nPIOIR Refer to Table 4-4 -- nPIOIW Refer to Table 4-4 -- -- SSPSCLK< 2> SSPSCLK< 2> -- Pu-1 Note[1] Note [5] Pu-1 Note[1] Note [5] -- Pu-1 Note[1] Note [5] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-13 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 5 of 17) VF-BGA Ball# (13x13) AC14 PBGA Ball# (23x23) Y12 Name Type Function After Reset GPIO<52> Primary Function CIF_DD<4> BB_OB_CLK FFRXD Secondary Alternate Function SSPSCLK<3> SSPSCLK<3> USB_P2_3 CIF_MCLK BB_OB_WAIT nPCE<2> Third Alternate Function -- -- -- SSPSYSCL K CIF_PCLK -- -- -- -- -- -- SSPTXD -- -- CIF_DD<5> FFDTR CIF_DD<4> FFRTS CIF_FV CIF_FV CIF_LV CIF_LV Reset State Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pu-1 Note[1] Pu-1 Note[1] Pu-1 Note[1] Pu-1 Note[1] Pu-1 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Sleep State GPIO<52 > GPIO<53 > GPIO<54 > GPIO<55 > GPIO<56 > GPIO<57 > GPIO<81 > GPIO<82 > GPIO<83 > GPIO<84 > GPIO<85 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Note [3] AB14 AA12 GPIO<53> BB_OB_STB -- Note [3] AA14 AB13 GPIO<54> Note [3] AA10 W9 GPIO<55> CIF_DD<1> -- nPWAIT USB_P3_4 nIOIS16 -- -- BB_IB_DAT<1> nPREG BB_IB_DAT<2> -- BB_IB_DAT<3> -- CIF_DD<0> BB_OB_DAT<0 > BB_IB_DAT<0> -- BB_IB_CLK FFTXD BB_IB_STB -- DREQ<2> BB_IB_WAIT Note [5] AB11 AB8 GPIO<56> Note [5] AC11 AB9 GPIO<57> Note [5] AB12 W10 GPIO<81> SSPTXD3 SSPRXD3 -- SSPSFRM3 SSPSFRM3 SSPSCLK3 SSPSCLK3 FFRXD nPCE<1> Note [3] AD9 AA8 GPIO<82> Note [3] AD10 AB10 GPIO<83> Note [3] AA11 Y10 GPIO<84> Note [3] AC12 VCC_LCD T24 AA10 GPIO<85> Note [3] P20 GPIO<14 > GPIO<19 > GPIO<58 > GPIO<59 > GPIO<60 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z GPIO<14> L_VSYNC -- SSPSCLK2 SSPSCLK2 -- -- -- -- -- -- SSPSFRM2 SSPSFRM2 -- L_CS LDD<0> LDD<0> LDD<1> LDD<1> LDD<2> LDD<2> -- UCLK FFRXD nURST -- -- -- -- -- -- Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] R22 P19 GPIO<19> Note [3] G24 G20 GPIO<58> Note [3] G22 H20 GPIO<59> Note [3] G23 G21 GPIO<60> Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-14 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 6 of 17) VF-BGA Ball# (13x13) H24 PBGA Ball# (23x23) F22 Name Type Function After Reset GPIO<61> Primary Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Secondary Alternate Function LDD<3> LDD<3> LDD<4> LDD<4> LDD<5> LDD<5> LDD<6> LDD<6> LDD<7> LDD<7> LDD<8> LDD<8> LDD<9> LDD<9> LDD<10> LDD<10> LDD<11> LDD<11> LDD<12> LDD<12> LDD<13> LDD<13> LDD<14> LDD<14> LDD<15> LDD<15> -- L_FCLK_RD -- L_LCLK _A0 -- L_PCLK_WR -- L_BIAS Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Sleep State GPIO<61 > GPIO<62 > GPIO<63 > GPIO<64 > GPIO<65 > GPIO<66 > GPIO<67 > GPIO<68 > GPIO<69 > GPIO<70 > GPIO<71 > GPIO<72 > GPIO<73 > GPIO<74 > GPIO<75 > GPIO<76 > GPIO<77 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Note [3] H22 G22 GPIO<62> Note [3] H23 J20 GPIO<63> Note [3] J22 H22 GPIO<64> Note [3] K24 K20 GPIO<65> Note [3] K22 J19 GPIO<66> Note [3] K23 K19 GPIO<67> Note [3] L21 K21 GPIO<68> Note [3] L23 J22 GPIO<69> Note [3] M24 K22 GPIO<70> Note [3] L22 L20 GPIO<71> Note [3] N24 L21 GPIO<72> Note [3] M22 L22 GPIO<73> Note [3] R23 N22 GPIO<74> Note [3] P23 N20 GPIO<75> Note [3] P22 N21 GPIO<76> Note [3] R21 P21 GPIO<77> Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-15 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 7 of 17) VF-BGA Ball# (13x13) N22 PBGA Ball# (23x23) M20 Name Type Function After Reset GPIO<86> Primary Function SSPRXD2 nPCE<1> nPCE<2> SSPTXD2 Secondary Alternate Function LDD<16> LDD<16> LDD<17> LDD<17> Third Alternate Function USB_P3_5 -- USB_P3_1 SSPSFRM2 Reset State Pd-0 Note[1] Pd-0 Note[1] Sleep State GPIO<86 > GPIO<87 > ICOC Z ICOC Z Note [3] N23 VCC_IO C11 M22 GPIO<87> Note [3] A8 GPIO<11 > GPIO<12 > ICOC Z ICOC Z EXT_SYNC<0> GPIO<11> CHOUT<0> EXT_SYNC<1> GPIO<12> CHOUT<1> CLK_EXT GPIO<13> SSPTXD2 GPIO<16> KP_MKIN<5> -- KP_MKIN<6> -- SSPEXTCLK2 SSPRXD2 PWM_OUT2 CIF_DD<7> PWM_OUT3 KP_DKIN<7> -- -- PWM_OUT<0> CIF_DD<6> PWM_OUT<1> SSPSCLKEN2 SSPSYSCLK2 SSPSCLK SSPSCLK SSPSFRM SSPSFRM -- SSPTXD CIF_PCLK -- SSPSCLKEN -- I2S_BITCLK -- I2S_SDATA_IN -- USB_P3_1 48_MHz -- 48_MHz KP_MKIN< 7> -- -- FFTXD -- -- SSPSCLK2 SSPSCLK2 -- -- -- -- -- -- FFCTS -- CIF_DD<0> FFRTS SSPSFRM SSPSFRM SSPSCLK SSPSCLK Pd-0 Note[1] Pd-0 Note[1] Note [3], Note[11 Note [3], Note[11 Note [3], Note[11 ] Note [3] B10 A7 C10 A6 GPIO<13 > GPIO<16 > GPIO<17 > GPIO<22 > GPIO<23 > GPIO<24 > GPIO<25 > GPIO<26 > GPIO<27 > GPIO<28 > GPIO<29 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] A18 C14 C16 D15 GPIO<17> Note [3] D13 A12 GPIO<22> KP_MKOUT<7 > -- CIF_MCLK CIF_FV CIF_FV CIF_LV CIF_LV SSPRXD -- Note [3] B16 A16 GPIO<23> Note [3] A17 B14 GPIO<24> Note [3] D16 A15 GPIO<25> Note [3] Note [3] B15 A14 GPIO<26> C15 C13 GPIO<27> SSPEXTCLK SSPSYSCLK AC97_BITCLK I2S_BITCLK AC97_SDATA_I N_0 SSPRXD2 Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] A14 D12 GPIO<28> Note [3] B13 A11 GPIO<29> Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-16 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 8 of 17) VF-BGA Ball# (13x13) PBGA Ball# (23x23) Name Type Function After Reset Primary Function -- GPIO<30> I2S_SDATA_O UT -- I2S_SYNC -- MSSCLK FFRXD USB_P2_2 FFCTS GPIO<35> -- FFDCD USB_P2_4 GPIO<37> FFDSR USB_P2_8 FFRI GPIO<38> SSPTXD3 KP_MKIN<4> USB_P2_6 SSPRXD2 GPIO<40> KP_MKOUT<6 > FFRXD GPIO<41> KP_MKOUT<7 > BTRXD -- -- ICP_TXD BTCTS -- -- GPIO<45> AC97_SYSCLK Secondary Alternate Function -- AC97_SDATA_ OUT -- AC97_SYNC -- MMCLK KP_MKIN<3> -- USB_P2_1 KP_MKOUT<6 > SSPSCLK2 SSPSCLK2 SSPSFRM2 SSPSFRM2 KP_MKIN<4> SSPTXD2 -- FFTXD -- FFDTR USB_P2_7 FFRTS ICP_RXD -- -- BTTXD -- -- -- BTRTS Third Alternate Function -- USB_P3_2 -- USB_P3_6 -- -- SSPSCLK3 SSPSCLK3 SSPSFRM3 SSPTXD3 KP_MKIN< 7> -- KP_MKIN< 3> FFTXD USB_P2_3 PWM_OUT <1> SSPSFRM3 SSPSFRM3 USB_P2_5 SSPSCLK3 SSPRXD3 -- -- CIF_MCLK CIF_FV CIF_FV CIF_LV CIF_LV CIF_PCLK SSPSYSCL K3 Reset State Sleep State C13 B11 GPIO<30 > GPIO<31 > GPIO<32 > GPIO<34 > GPIO<35 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] C12 C11 GPIO<31> Note [3] A20 C16 GPIO<32> Note [3] A21 B19 GPIO<34> Note [3] B19 D17 Note [3] C14 B13 GPIO<36 > ICOC Z GPIO<36> Pd-0 Note[1] Note [3] A15 D13 GPIO<37 > ICOC Z Pd-0 Note[1] Note [3] B14 A13 GPIO<38 > GPIO<39 > GPIO<40 > ICOC Z ICOC Z ICOC Z Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] D19 B17 GPIO<39> Note [3] D14 C12 Note [3] C18 A19 GPIO<41 > GPIO<42 > GPIO<43 > GPIO<44 > GPIO<45 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] C21 D20 GPIO<42> Note [3] C22 B21 GPIO<43> Note [3] B20 A20 GPIO<44> Note [3] C19 C17 Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-17 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 9 of 17) VF-BGA Ball# (13x13) B11 PBGA Ball# (23x23) A9 Name Type Function After Reset GPIO<46> Primary Function ICP_RXD -- CIF_DD<0> Secondary Alternate Function STD_RXD PWM_OUT<2> -- ICP_TXD SSPRXD2 -- -- USBHPEN<1> -- MSBS CIF_DD<6> -- CIF_DD<5> -- CIF_DD<4> -- MBREQ DVAL<1> Third Alternate Function -- -- -- PWM_OUT <3> SSPSFRM2 SSPSFRM2 FFRI SSPTXD2 -- -- -- -- -- -- KP_MKIN< 6> -- FFRXD KP_MKOUT <6> KP_MKIN< 3> -- KP_MKIN< 4> FFRTS KP_MKIN< 5> FFTXD FFCTS -- -- -- FFRXD -- Reset State Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Sleep State GPIO<46 > GPIO<47 > GPIO<88 > GPIO<89 > GPIO<92 > GPIO<93 > GPIO<94 > ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z Note [3] A11 C10 GPIO<47> STD_TXD USBHPWR<1> -- SSPRXD3 AC97_SYSCLK MMDAT<0> MMDAT<0> KP_DKIN<0> Note [3] C23 C22 GPIO<88> Note [3] D22 C21 GPIO<89> Note [3] A19 A18 GPIO<92> Note [3] AB19 Y16 GPIO<93> AC97_SDATA_ OUT KP_DKIN<1> AC97_SYNC KP_DKIN<2> Note [3] AD19 AA17 GPIO<94> Note [3] AA18 AB18 GPIO<95 > ICOC Z GPIO<95> AC97_RESET_ n KP_DKIN<3> Pd-0 Note[1] Note [3] AC19 W16 GPIO<96 > ICOC Z GPIO<96> Pd-0 Note[1] Note [3] AA17 Y15 GPIO<97 > ICOC Z GPIO<97> KP_DKIN<4> -- DREQ<1> MBGNT CIF_DD<0> -- AC97_SDATA_I N_1 -- DREQ<2> -- -- -- -- -- Pd-0 Note[1] Note [3] AD18 AA16 GPIO<98 > ICOC Z GPIO<98> KP_DKIN<5> AC97_SYSCLK Pd-0 Note [1] Note [3] AB18 AB17 GPIO<99 > GPIO<10 0> GPIO<10 1> GPIO<10 2> ICOC Z ICOC Z ICOC Z ICOC Z GPIO<99> KP_DKIN<6> -- Pd-0 Note [1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] AC18 AA15 GPIO<100> KP_MKIN<0> -- KP_MKIN<1> -- KP_MKIN<2> nPCE<1> Note [3] AC17 AB16 GPIO<101> Note [3] AB17 Y14 GPIO<102> Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-18 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 10 of 17) VF-BGA Ball# (13x13) PBGA Ball# (23x23) Name Type Function After Reset Primary Function CIF_DD<3> GPIO<103> -- CIF_DD<2> GPIO<104> PSKTSEL CIF_DD<1> GPIO<105> nPCE<2> CIF_DD<9> GPIO<106> -- CIF_DD<8> GPIO<107> -- CIF_DD<7> GPIO<108> CHOUT<0> MMDAT<1> MMDAT<1> MMDAT<2>/ MMCCS<0> MMDAT<2>/ MMCCS<0> MMDAT<3>/ MMCCS<1> MMDAT<3>/ MMCCS<1> MMCMD MMCMD -- GPIO<113> I2S_SYSCLK CIFDD_<1> Secondary Alternate Function -- KP_MKOUT<0 > -- KP_MKOUT<1 > -- KP_MKOUT<2 > -- KP_MKOUT<3 > -- KP_MKOUT<4 > -- KP_MKOUT<5 > MSSDIO MSSDIO -- -- -- -- nMSINS -- -- AC97_RESET_ n -- UVS0 Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- USB_P3_3 -- -- -- MBREQ PWM_OUT <1> Reset State Sleep State AC16 AB15 GPIO<10 3> ICOC Z Pd-0 Note[1] Note [3] AD15 W14 GPIO<10 4> ICOC Z Pd-0 Note[1] Note [3] AB16 Y13 GPIO<10 5> ICOC Z Pd-0 Note[1] Note [3] AB15 W13 GPIO<10 6> ICOC Z Pd-0 Note[1] Note [3] AC15 AB14 GPIO<10 7> ICOC Z Pd-0 Note[1] Note [3] AD14 AA13 GPIO<10 8> GPIO<10 9> ICOC Z ICOC Z Pd-0 Note[1] Pd-0 Note[1] Note [3] D17 D16 GPIO<109> Note [3] B17 C15 GPIO<11 0> ICOC Z GPIO<110> Pd-0 Note[1] Note [3] C17 A17 GPIO<11 1> ICOC Z GPIO<111> Pd-0 Note[1] Note [3] B18 B16 GPIO<11 2> GPIO<11 3> GPIO<11 4> Note [17] GPIO<11 5> Note [17] ICOC Z ICOC Z ICOC Z ICOC Z GPIO<112> Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pu-1 Note[1] Note [3] A13 A10 Note [3] D24 F19 GPIO<114> Note [17] GPIO<115> Note [17] Note [3] DREQ<0> UEN CIF_DD<3> nUVS1 E21 E21 Note [3] NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-19 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 11 of 17) VF-BGA Ball# (13x13) PBGA Ball# (23x23) Name Type Function After Reset Primary Function CIF_DD<2> DVAL<0> SCL D20 C18 GPIO<11 7> ICOC Z GPIO<117> SCL SDA A22 B20 GPIO<11 8> ICOC Z GPIO<118> SDA Secondary Alternate Function AC97_SDATA_I N_0 nUVS2 -- -- -- -- Third Alternate Function UDET MBGNT -- -- -- -- Reset State Sleep State C24 E20 GPIO<11 6> ICOC Z GPIO<116> Pu-1 Note[1] Note [3] Note [3], Note[12 ] Note [3], Note[12 ] Pu-1 Note[1] Pu-1 Note[1] VCC_USB B22 C20 E22 D23 VCC_USIM F22 H19 GPIO<90 > GPIO<91 > UIO ICOC Z ICOC Z ICOC Z GPIO<90> KP_MKIN<5> -- KP_MKIN<6> -- UIO USB_P3_5 nURST USB_P3_1 UCLK -- CIF_DD<4> -- CIF_DD<5> -- -- Pd-0 Note[1] Pd-0 Note[1] Driven Low Note [3] D18 E19 E22 D22 USBC_P USBC_N USBH_P <1> USBH_N <1> IAOA Z IAOA Z IAOA Z IAOA Z USBC_P USBC_N USBH_P<1 > USBH_N<1 > USBC_P USBC_N USBH_P<1> USBH_N<1> -- -- -- -- -- -- -- -- Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z F23 E23 VCC_REG V22 Y24 W21 W23 U22 G19 F20 GPIO<91> UIO Note [3] Hi-Z U20 U21 V22 T19 T22 GPIO<0> GPIO<1> GPIO<3> GPIO<4> GPIO<9> Note [18] GPIO<10 > Note [18] ICOC Z ICOC Z ICOC Z ICOC Z ICOC Z GPIO<0> GPIO<1> GPIO<3> GPIO<4> GPIO<9> Note [18] GPIO<10> Note [18] GPIO<0> GPIO<1> PWR_SCL PWR_SDA -- HZ_CLK FFDCD HZ_CLK -- -- -- -- -- -- -- -- -- -- -- -- FFCTS CHOUT<0> USB_P3_5 CHOUT<1> Pd-0 Note[1] Pu-1 Note[1] Pu-1 Note[1] Pu-1 Note[1] Pd-0 Note[1] Pd-0 Note[1] Pd-0 Note[1] Note [3] Note [7] Hi-Z Hi-Z Note [7] Note [7] Note [7] V23 U22 ICOC Z NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-20 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 12 of 17) VF-BGA Ball# (13x13) W24 Y22 Y21 AB23 Y23 AB24 W22 AA24 AB21 AD22 AC22 AA20 U21 U23 V24 T21 T22 T23 VCC_OSC AC21 AD21 AA22 AA23 AB22 AB20 AA20 Y21 Y22 W19 PXTAL_I N PXTAL_O UT TXTAL_I N TXTAL_O UT PWR_OU T IA OA IA OA OA PXTAL_IN PXTAL_OU T TXTAL_IN TXTAL_OU T PWR_OUT PXTAL_IN PXTAL_OUT TXTAL_IN TXTAL_OUT PWR_OUT -- -- -- -- -- -- -- -- -- -- Note[2] Note[2] Note[2] Note[2] Hi-Z Note [2] Note [2] Note [2] Note [2] Hi-Z PBGA Ball# (23x23) T21 W20 W21 V19 W22 U19 V20 V21 Y19 AA21 Y18 W17 T20 R22 R21 R20 R19 P22 Name CLK_RE Q NRESET NRESET _OUT BOOT_S EL PWR_EN NBATT_F AULT NVDD_F AULT SYS_EN PWR_CA P<0> PWR_CA P<1> PWR_CA P<2> PWR_CA P<3> NTRST TDI TDO TMS TCK TESTCLK Type ICOC Z IC OC IC OC IC IC ICOC Z OA OA OA OA IC IC OCZ IC IC IC Function After Reset CLK_REQ nRESET nRESET_O UT BOOT_SEL PWR_EN nBATT_FAU LT nVDD_FAU LT SYS_EN -- -- -- -- nTRST TDI TDO TMS TCK TESTCLK Primary Function CLK_REQ nRESET nRESET_OUT BOOT_SEL PWR_EN nBATT_FAULT nVDD_FAULT SYS_EN PWR_CAP<0> PWR_CAP<1> PWR_CAP<2> PWR_CAP<3> nTRST TDI TDO TMS TCK TESTCLK Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Pu-1 Input Note [9] Low Input Note[16] Low Low -- -- -- -- -- Input Note [9] Input Note [9] Hi-Z Input Note [9] Input Pd-0 Sleep State Note [8] Input Note [8] Input Note [8] Input Input Note [7] Note [7] Note [7] Note [7] Note [7] Input Input Hi-Z Input Input Input NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-21 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 13 of 17) VF-BGA Ball# (13x13) SUPPLIES AB20 A12 AD17 A16 B24 A24 A23 B23 P24 J24 P1 C3 E2 L3 AD2 AC2 AC1 AD1 M1 H1 F1 AD8 Y17 B10 W15 D14 A21 A22 B22 D19 M19 J21 B2 C3 C6 C9 F3 H3 K3 M3 P3 T3 V3 Y3 VCC_BAT T VCC_IO VCC_IO VCC_IO VCC_US B VCC_US B VCC_US B VCC_US B VCC_LC D VCC_LC D VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS VCC_BATT VCC_IO VCC_IO VCC_IO VCC_USB VCC_USB VCC_USB VCC_USB VCC_LCD0 VCC_LCD1 VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_BATT VCC_IO VCC_IO VCC_IO VCC_USB VCC_USB VCC_USB VCC_USB VCC_LCD VCC_LCD VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input PBGA Ball# (23x23) Name Type Function After Reset Primary Function Secondary Alternate Function Third Alternate Function Reset State Sleep State NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-22 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 14 of 17) VF-BGA Ball# (13x13) U2 AA2 AC8 B8 A4 AC6 W2 AD12 AC20 A9 A8 A5 B4 B12 A7 D3 J23 L24 F24 AD16 R24 M23 B21 PBGA Ball# (23x23) Y5 Y7 Y9 AA2 N/A N/A N/A AA11 AB19 B4 B7 B8 C5 D11 E6 E8 F5 H5 L4 E15 E17 F18 H18 Name VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_ME M VCC_BB VCC_PLL VCC_SR AM VCC_SR AM VCC_SR AM VCC_SR AM VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE Type Function After Reset VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_BB VCC_PLL VCC_SRA M VCC_SRA M VCC_SRA M VCC_SRA M VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E Primary Function VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_MEM VCC_BB VCC_PLL VCC_SRAM VCC_SRAM VCC_SRAM VCC_SRAM VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Sleep State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-23 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 15 of 17) VF-BGA Ball# (13x13) W3 AD4 T2 AD11 N/A N/A N/A N/A N/A N/A E24 AA21 AC24 AD24 AC23 AD23 V21 D11 AA19 D15 N21 AA16 H21 F21 D18 U24 D5 F4 PBGA Ball# (23x23) L19 R5 U5 V6 V8 W11 R18 U18 V15 V17 F21 W18 Y20 AA22 AB21 AB22 N/A B12 B15 B18 D21 H21 M21 N19 AA14 AA18 A1 A2 Name VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_CO RE VCC_USI M VSS VSS VSS VSS VSS VSS VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_ME M VSS_ME M Type Function After Reset VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_COR E VCC_USIM VSS VSS VSS VSS VSS VSS VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_MEM VSS_MEM Primary Function VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_USIM VSS VSS VSS VSS VSS VSS VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_MEM VSS_MEM Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Sleep State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-24 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 16 of 17) VF-BGA Ball# (13x13) H4 J4 AC3 AB2 L4 T4 V4 AA5 AA8 AA9 D9 N4 R2 C5 Y4 AA13 AD20 B2 A2 B1 A1 J21 D10 PBGA Ball# (23x23) B1 B3 B6 B9 F2 H2 L2 P2 T2 V2 AA1 AA6 AA9 AB1 AB2 AB11 AA19 E5 E7 E9 G5 J5 E14 Name VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_ME M VSS_BB VSS_PLL VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE Type Function After Reset VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_BB VSS_PLL VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Primary Function VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_MEM VSS_BB VSS_PLL VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Sleep State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. Electrical, Mechanical, and Thermal Specification 4-25 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Use Summary (Sheet 17 of 17) VF-BGA Ball# (13x13) AA15 M21 U3 AA7 P21 K21 G21 D21 D12 D8 W4 AA12 B5 D7 PBGA Ball# (23x23) E16 E18 G18 J18 P5 T5 V5 V7 V9 P18 T18 V14 V16 V18 Name VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE VSS_CO RE Type Function After Reset VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Primary Function VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Secondary Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- Third Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset State Input Input Input Input Input Input Input Input Input Input Input Input Input Input Sleep State Input Input Input Input Input Input Input Input Input Input Input Input Input Input PS PS PS PS PS PS PS PS PS PS PS PS PS PS NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. 4-26 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions 4.3 Note Signal Types Description GPIO reset/deep sleep operation: After any reset is asserted or if the PXA270 processor is in deep sleep mode, these pins are configured as GPIO inputs by default. The input buffers for these pins are disabled to prevent current drain and must be enabled prior to use by clearing the read disable hold bit, PSSR[RDH]. Until RDH is cleared, each pin is pulled high (Pu-1), pulled low (Pd-0), or floated (Hi-Z). Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators and are not affected by either reset or sleep. For more information, see the "Clocks and Power" chapter in the Intel(R) PXA27x Processor Family Developer's Manual. GPIO sleep operation: During the transition into sleep mode, the configuration of these pins is determined by the corresponding GPIO setting. This pin is not driven during sleep if the direction of the pin is selected to be an input. If the direction of the pin is selected as an output, the value contained in the Power Manager GPIO Sleep-State register (PGSR0/1/2/3) is driven out onto the pin and held while the PXA270 processor is in sleep mode. Upon exit from sleep mode, GPIOs that are configured as outputs continue to hold the standby, sleep, or deep-sleep state until software clears the peripheral control hold bit, PSSR[PH]. Software must clear this bit (by writing 0b1 to it) after the peripherals have been fully configured, as described in Note[1], but before the process actually uses them. GPIOs that are configured as inputs immediately after exiting sleep mode cannot be used until PSSR[RDH] is cleared. Static memory control pins: During sleep mode, these pins can be programmed either to drive the value in the Power Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state, software must set PCFR[FS]. If FS is not set, these pins function as described in Note[3] during the transition to sleep mode. PCMCIA control pins: During sleep mode, these pins can be programmed either to drive the value in the Power Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state, software must set PCFR[FP]. If FP is not set, these pins function as described in Note[3] during the transition to sleep mode. (reserved) When the power manager overrides the GPIO alternate function, the Power Manager GPIO Sleep-State registers (PGSR0/1/2/3) and the PSSR[RDH] bit are ignored. Pullup and pulldown are disabled immediately after the power manager overrides the GPIO function. Output functions during sleep mode Pull-up always enabled (reserved) Pins do not function during sleep mode if the OS timer is active Pins must be floated by software during sleep mode (floating does not happen automatically) (reserved) (reserved) The pin is three-stateable (Hi-Z) based on the value of PCFR[FS]. There is no PGSR0/1/2/3 setting associated with the pin because it is not a GPIO. PWR_EN goes high during reset, between the assertion of the reset pin and the de-assertion of internal reset within the PXA270 processor, after SYS_EN is driven high. GPIOs 114 and115: The alternate function configuration of these pins is ignored when either PUCR[USIM114] or PUCR[USIM115] bits are set. Setting these bits forces the USIM enable signal onto these GPIOs. When software sets the OSCC[PIO_EN] or OSCC[TOUT_EN] bits, then any GPIO alternate function setting applied to GPIO<9> or GPIO <10> is overridden with the CLK_PIO function on GPIO<9> and CLK_TOUT on GPIO<10>. Refer to Table 4-4. Table 4-2. Pin Use and Mapping Notes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Electrical, Mechanical, and Thermal Specification 4-27 Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-3. Signal Types Type IC OC OCZ ICOCZ IA OA IAOA IAOAZ PS CMOS input CMOS output CMOS output, three-stateable CMOS bidirectional, three-stateable Analog input Analog output Analog bidirectional Analog bidirectional - three-stateable Power supply Description 4.4 Memory Controller Reset and Initialization On reset, the SDRAM interface is disabled. Reset values for the boot ROM are determined by BOOT_SEL (see the Intel(R) PXA27x Processor Family Developers Manual, Memory Controller chapter). Boot ROM is immediately available for reading upon exit from reset, and all memory interface control registers are available for writing. On hardware reset, the memory pins and controller are in the state shown in Table 4-4. Table 4-4. Memory Controller Pin Reset Values (Sheet 1 of 2) Pin Name SDCLK <3 1:0> SDCKE DQM <3:0> nSDCS <3:2> nSDCS <1:0> nWE nSDRAS nSDCAS nOE MA <25:0> RDnWR MD <31:0> nCS <0> nCS <5:1> nPIOIR nPIOIW Reset, Sleep, Standby, Deep-Sleep, Frequency Change, and Manual Self-Refresh Mode Values 0b000 0 0b0000 GPIO (memory controller drives 0b11) 0b11 1 1 1 1 0x0000_00001 0 0x0000_00002 1 GPIO (memory controller drives 0b11111) GPIO (memory controller drives high) GPIO (memory controller drives high) 4-28 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Pin Listing and Signal Definitions Table 4-4. Memory Controller Pin Reset Values (Sheet 2 of 2) Pin Name nPOE nPWE Reset, Sleep, Standby, Deep-Sleep, Frequency Change, and Manual Self-Refresh Mode Values GPIO (memory controller drives high) GPIO (memory controller drives high) NOTE: This indicates that the GPIO pin, if configured for the alternate function used by the memory controller during reset, drives the represented value. NOTE: SCLK<3> is only available on PXA270 processor family packages 1. MA pins are driven 2. MD pins are pulled low The address signals are driven low and data signals are pulled low during sleep, standby, deepsleep, frequency-change modes, and manual self-refresh. All other memory control signals are in the same state that they are in after a hardware reset. If the SDRAMs are in self-refresh mode, they are kept there by driving SDCKE low. 4.5 Power-Supply Pins Table 4-5 summarize the power-supply ball count. Table 4-5. Discrete (13x13 VF-BGA) Power Supply Pin Summary Name VCC_BATT VCC_IO VCC_USB VCC_LCD VCC_MEM VCC_BB VCC_PLL VCC_SRAM VCC_CORE VCC_USIM VSS VSS_IO VSS_MEM VSS_BB VSS_PLL VSS_CORE Number of Package Balls 13x13 mm VF-BGA 1 3 4 2 19 1 1 4 14 1 6 9 17 1 1 56 Number of Pachage Balls 23x23 mm PBGA 1 3 4 2 16 1 1 4 20 1 5 9 17 1 1 56 Electrical, Mechanical, and Thermal Specification 4-29 Intel(R) PXA270 Processor Pin Listing and Signal Definitions 4-30 Electrical, Mechanical, and Thermal Specification Electrical Specifications 5.1 Absolute Maximum Ratings 5 The absolute maximum ratings (shown in Table 5-1) define limitations for electrical and thermal stresses. These limits prevent permanent damage to the Intel(R) PXA270 processor. Note: Absolute maximum ratings are not operating ranges. Table 5-1. Absolute Maximum Ratings Symbol TS VCC_OL1 VCC_OL2 VCC_OH1 VCC_OH2 VCC_OH3 VCC_HV VCC_LV VIP VIP_X Description Storage temperature Offset voltage between any of the following pins: VCC_CORE Offset voltage between any of the following pins: VCC_SRAM Offset voltage between any of the following pins: VCC_MEM Offset voltage between any of the following pins: VCC_IO Offset voltage between VCC_LCD<0> and VCC_LCD<1> Voltage applied to high-voltage supply pins (VCC_BB, VCC_USB, VCC_USIM, VCC_MEM, VCC_IO<, VCC_LCD) Voltage applied to low-voltage supply pins (VCC_CORE, VCC_PLL, VCC_SRAM) Voltage applied to non-supply pins except PXTAL_IN, PXTAL_OUT, TXTAL_IN, and TXTAL_OUT pins Voltage applied to XTAL pins (PXTAL_IN, PXTAL_OUT, TXTAL_IN, TXTAL_OUT) Maximum ESD stress voltage, three stresses maximum: * Any pin to any supply pin, either polarity, or * Any pin to all non-supply pins together, either polarity Maximum DC input current (electrical overstress) for any non-supply pin Min -40 -0.3 -0.3 -0.3 -0.3 -0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 Max 125 0.3 0.3 0.3 0.3 0.3 VSS+4.0 VSS+1.45 VSS+4.0 VSS+1.45 Units C V V V V V V V V V VESD -- 2000 V IEOS -- 5 mA 5.2 Operating Conditions This section shows operating voltage, frequency, and temperature specifications for the PXA270 processor. Electrical, Mechanical, and Thermal Specification 5-1 Intel(R) PXA270 Processor Electrical Specifications Table 5-2 shows each power domains supported voltages (except for VCC_MEM and VCC_CORE). Table 5-3 shows all of the supported memory voltages and frequency operating ranges (VCC_MEM). Table Note: shows all of the supported core voltage and frequency ranges (VCC_CORE). The operating temperature specification is a function of voltage and frequency. Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2) Symbol Description Min Typical Max Units Operating Temperature Package operating temperature (Standard Temp) Package operating temperature (Extended Temp - PBGA ONLY) Junction-to-case temperature gradient (VF-BGA) Junction-to-case temperature gradient (PBGA) -25 -40 -- -- -- -- 2 1.4 +85 C +85 -- -- Tcase Theta Jc C / watt VCC_BATT Voltage VVCC0 Voltage applied on VCC_BATT @3.0V Voltage difference between VCC_BATT and VCC_IO during power-on reset or deep-sleep wake-up (from the assertion of SYS_EN to the de-assertion of nRESET_OUT) Voltage difference between VCC_BATT and VCC_IO when VCC_IO is enabled Ramp Rate 2.25 3.00 3.75 V VVDF1 0 -- 0.30 V VVDF2 Tbramp 0 -- -- 10 0.20 12 V mV/uS VCC_PLL Voltage VVCC1 Tpwrramp Voltage applied on VCC_PLL @1.3V (+10 / -10%) Ramp Rate 1.17 -- 1.30 10 1.43 12 V mV/uS VCC_BB Voltages VVCC2a VVCC2b VVCC2c VVCC2d Tsysramp Voltage applied on VCC_BB @1.8V (+20 / -5%) Voltage applied on VCC_BB @2.5V (+10 / -10%) Voltage applied on VCC_BB @3.0V (+10 / -10%) Voltage applied on VCC_BB @3.3V (+10 / -10%) Ramp Rate 1.71 2.25 2.70 2.97 -- 1.80 2.50 3.0 3.3 10 2.16 2.75 3.30 3.63 12 V V V V mV/uS NOTE: VCC_BB may optionally be tied to the same PMIC regulator as VCC_IO if the system design allows both VCC_IO and VCC_BB to use the same voltage level. This allows the GPIO's on VCC_BB to be used at the same voltage level. VCC_LCD Voltages 5-2 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Electrical Specifications Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2) Symbol VVCC3a VVCC3b VVCC3c VVCC3d Tsysramp Description Voltage applied on VCC_LCD @1.8V (+20 / -5%) Voltage applied on VCC_LCD @2.5V (+10 / -10%) Voltage applied on VCC_LCD @3.0V (+10 / -10%) Voltage applied on VCC_LCD @3.3V (+10 / -10%) Ramp Rate Min 1.71 2.25 2.70 2.97 -- Typical 1.80 2.50 3.0 3.3 10 Max 2.16 2.75 3.30 3.63 12 Units V V V V mV/uS VCC_IO Voltages VVCC4a VVCC4b Tsysramp Voltage applied on VCC_IO @3.0V (+10 / -10.3%) Voltage applied on VCC_IO @3.3V (+10 / -10%) Ramp Rate 2.69175 2.97 -- 3.0 3.3 10 3.30 3.63 12 V V mV/uS NOTE: VCC_IO must be maintained at a voltage as high as or higher than, all other supplies except for VCC_BATT and VCC_USB VCC_USIM Voltages VVCC5a VVCC5b Tsysramp Voltage applied on VCC_USIM @1.8V (+20 / -5%) Voltage applied on VCC_USIM @3.0V (+10 / -10%) Ramp Rate 1.71 2.70 -- 1.80 3.0 10 2.16 3.30 12 V V mV/uS NOTE: If the system does NOT use the USIM module, VCC_USIM can be tied to VCC_IO (at any supported VCC_IO voltage level). This allows the GPIO's on VCC_USIM to be used at the same voltage level as VCC_IO GPIO's. NOTE: Software must NOT configure USIM signals to be used if this is done. VCC_SRAM Voltage VVCC6 Tpwrramp Voltage applied on VCC_SRAM @1.1V (+10 / -10%) Ramp Rate 0.99 -- 1.10 10 1.21 12 V mV/uS VCC_USB Voltage VVCC7a VVCC7b Tsysramp Voltage applied on VCC_USB @3.0V (+10 / -10%) Voltage applied on VCC_USB @3.3V (+10 / -10%) Ramp Rate 2.70 2.97 -- 3.00 3.30 10 3.30 3.63 12 V V mV/uS System design must ensure that the device case temperature is maintained within the specified limits. In some system applications it may be necessary to use external thermal management (for example, a package-mounted heat spreader) or configure the device to limit power consumption and maintain acceptable case temperatures. Table 5-3 shows the supported memory frequency and memory supply voltage operating ranges for the PXA270 processor. Electrical, Mechanical, and Thermal Specification 5-3 Intel(R) PXA270 Processor Electrical Specifications Table 5-3. Memory Voltage and Frequency Electrical Specifications Symbol Description Min Typical Max Units Memory Voltage and Frequency Range 1 VMEM1 fSM1A fSM1B Tsysramp Voltage applied on VCC_MEM External synchronous memory frequency, SDCLK1, SDCLK2 External synchronous memory frequency, SDCLK0 Ramp Rate 1.71 13 13 -- 1.80 -- -- 10 2.16 104 104 12 V MHz MHz mV/uS Memory Voltage and Frequency Range 2 VMEM2 fSM2A fSM2B Tsysramp Voltage applied on VCC_MEM External synchronous memory frequency, SDCLK1, SDCLK2 External synchronous memory frequency, SDCLK0 Ramp Rate 2.25 13 13 -- 2.50 -- -- 10 2.75 104 104 12 V MHz MHz mV/uS Memory Voltage and Frequency Range 3 VMEM3 fSM3A fSM3B Tsysramp Voltage applied on VCC_MEM External synchronous memory frequency, SDCLK1, SDCLK2 External synchronous memory frequency, SDCLK0 Ramp Rate 2.70 13 13 -- 3.0 -- -- 10 3.3 104 104 12 V MHz MHz mV/uS Memory Voltage and Frequency Range 4 VMEM4 fSM4A fSM4B Tsysramp Voltage applied on VCC_MEM External synchronous memory frequency, SDCLK1, SDCLK2 External synchronous memory frequency, SDCLK0 Ramp Rate 2.97 13 13 -- 3.30 -- -- 10 3.63 104 104 12 V MHz MHz mV/uS Table 5-4 shows the supported core frequency and core supply voltage operating ranges for the PXA270 processor. Each frequency range is specified in the following format: (core frequency/internal system bus frequency/memory controller frequency/SDRAM frequency) Note: Refer to the "Clocks and Power" section of the Intel(R) PXA27x Processor Family Developers Manual for supported frequencies, clock register settings as listed in Table 5-4. Table 5-4. Core Voltage and Frequency Electrical Specifications (Sheet 1 of 2) Symbol Description Min Typical Max Units Core Voltage and Frequency Range 1 (13/13/13/13 CCCR[CPDIS]=1, CCCR[PPDIS]=1) VVCCC1 fCORE1 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 0.8075 13 -- 0.85 -- 10 1.705 13 12 V MHz mV/uS 5-4 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Electrical Specifications Table 5-4. Core Voltage and Frequency Electrical Specifications (Sheet 2 of 2) Core Voltage and Frequency Range 2 (13/13/13/13 CCCR[CPDIS]=1, CCCR[PPDIS]=0), (91/45.5/91/45.5), and (104/104/104/104) VVCCC2 fCORE2 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 0.855 91 -- 0.9 -- 10 1.705 104 12 V MHz mV/uS Core Voltage and Frequency Range 3 (156/104/104/104) VVCCC3 fCORE3 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 0.95 -- -- 1.00 156 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 4 (208/208/208/104) and (208/208/104/104) VVCCC4 fCORE4 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 1.12 -- -- 1.18 208 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 4a (208/104/104/104) VVCCC4a fCORE4a Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 0.9975 -- -- 1.05 208 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 5 (312/208/208/104) and (312/208/104/104) VVCCC5 fCORE5 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 1.1875 -- -- 1.25 312 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 5a (312/104/104/104) VVCCC5a fCORE5a Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 0.99 -- -- 1.1 312 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 6 (416/208/208/104) amd (416/208/104/104) VVCCC6 fCORE6 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 1.2825 -- -- 1.35 416 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 7 (520/208/208/104) and (520/208/104/104) VVCCC7 fCORE7 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 1.3775 -- -- 1.45 520 10 1.705 -- 12 V MHz mV/uS Core Voltage and Frequency Range 8 (624/208/208/104) and (624/208/104/104) VVCCC8 fCORE8 Tpwrramp Voltage applied on VCC_CORE Core operating frequency Ramp Rate 1.4725 -- -- 1.55 624 10 1.705 -- 12 V MHz mV/uS Core operating frequency not offered in PBGA package. Electrical, Mechanical, and Thermal Specification 5-5 Intel(R) PXA270 Processor Electrical Specifications 5.2.1 Internal Power Domains The external power supplies are used to generate several internal power domains, which are shown in Table 5-5. Refer to the Power Manager / Internal Power Domain Block Diagram in the "Clocks and Power" section of the Intel(R) PXA27x Processor Family Developers Manual for more information on internal power domains. Table 5-5. Internally Generated Power Domain Descriptions Name VCC_REG VCC_OSC VCC_RTC VCC_PI VCC_CPU VCC_PER VCC_Rx Units IO associated with deep-sleepactive units Oscillator power supplies RTC and power manager supply Power manager I 2C supply CPU core Peripheral units Particular internal SRAM unit Generation Switched between VCC_BATT and VCC_IO Generated from VCC_REG Switched between VCC_OSC and VCC_CORE Switched between VCC_OSC and VCC_CORE Independent power-down from VCC_CORE Independent power-down from VCC_CORE Switched between VCC_OSC and VCC_SRAM Tolerance +/- 30% - Table 5-6 shows the recommended core voltage specification for each of the lower power modes. Table 5-6. Core Voltage Specifications For Lower Power Modes Mode Standby Deep-Idle Description Voltage applied on VCC_CORE Voltage applied on VCC_CORE Min 1.045 0.8075 Typical 1.1 0.85 Max 1.21 0.935 Units V V 5.3 Power-Consumption Specifications Power consumption depends on the operating voltage and frequency, peripherals enabled, external switching activity, and external loading and other factors. Table 5-7 contains three sets of power consumption information: Active Power Consumption, Idle Power Consumption, and Low-Power Modes Power Consumption. The data set are projected numbers based off of measured data at room temperature. For Active Power Consumption data, no peripherals are enabled except for UART. Use these specifications as a guideline for power consumption capacity. These typical guidelines vary across different platforms and software applications. 5-6 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Electrical Specifications Table 5-7. Power-Consumption Specifications (Sheet 1 of 2) Parameter Description Active Power Consumption 624 MHz Active Power (208 MHz System bus) 925 mW VCC_CORE = 1.55V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.45V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.35V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.25V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.1V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.15V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 0.9V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 0.85V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Typical Units Conditions 520 MHz Active Power (208 MHz System bus) 747 mW 416 MHz Active Power (208 MHz System bus) 570 mW 312 MHz Active Power (208 MHz System bus) 390 mW 312 MHz Active Power (104 MHz System bus) 375 mW 208 MHz Active Power (208 MHz System bus) 279 mW 104 MHz Active Power (104 MHz System bus) 116 mW 13 MHz Active Power (CCCR[CPDIS=1) Idle Power Consumption 624 MHz Idle Power (208 MHz System bus) 44.2 mW 260 mW VCC_CORE = 1.55V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.45V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.35V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.25V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.1V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 1.15V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE = 0.9V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 520 MHz Idle Power (208 MHz System bus) 222 mW 416 MHz Idle Power (208 MHz System bus) 186 mW 312 MHz Idle Power (208 MHz System bus) 154 mW 312 MHz Idle Power (104 MHz System bus) 109 mW 208 MHz Idle Power (208 MHz System bus) 129 mW 104 MHz Idle Power (104 MHz System bus) 64 mW Electrical, Mechanical, and Thermal Specification 5-7 Intel(R) PXA270 Processor Electrical Specifications Table 5-7. Power-Consumption Specifications (Sheet 2 of 2) Parameter Description Low Power modes Power Consumption 13 MHz Idle Mode1 Power (LCD on) 15.4 mW VCC_CORE, VCC_SRAM, VCC_PLL = 0.85V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE, VCC_SRAM, VCC_PLL = 0.85V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE, VCC_SRAM, VCC_PLL = 0V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE, VCC_SRAM, VCC_PLL = 0V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V VCC_CORE, VCC_SRAM, VCC_PLL = 1.1V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Typical Units Conditions 13 MHz Idle Mode1 Power (LCD off) 8.5 mW Deep-Sleep mode 0.1014 mW Sleep mode 0.1630 mW Standby mode 1.7224 mW NOTE: 1) 13 MHz Idle Mode (CCCR[CPDIS] =1 (CCCR[PPDIS] = 1) 5.4 DC Specification The DC characteristics for each pin include input sense levels, output drive levels, and currents. These parameters can be used to determine maximum DC loading and to determine maximum transition times for a given load. Table 5-8 shows the DC operating conditions for the high- and low-strength input, output, and I/O pins. Note: VCC_IO must be maintained at a voltage as high as or higher than all other supplies except VCC_BATT and VCC_USB and VCC_USB. Table 5-8. Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet 1 of 2) Symbol Description Min Max Unit s Testing Conditions / Notes Input DC Operating Conditions (VCC = 1.8V, 2.5, 3.0, 3.3 Typical) VIH1 Input high voltage, all standard input and I/O pins, relative to applicable VCC (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, or VCC_USIM) Input low voltage, all standard input and I/O pins, relative to applicable VSS (VSS_IO, VSS_MEM, or VSS_BB) and VCC (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, or VCC_USIM) DC Overshoot voltage / duration DC Undershoot voltage / duration 0.8 * VCC VCC + 0.1 V -- VIL1 VSS - 0.1 0.2 * VCC V -- OS US -- -- +1 -1 V V Max duration of 4nS Max duration of 4nS Output DC Operating Conditions (VCC = 1.8, 2.5, 3.0, 3.3 Typical) 5-8 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Electrical Specifications Table 5-8. Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet 2 of 2) Symbol Description Output high voltage, all standard output and I/ O pins, relative to applicable VCC (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, or VCC_USIM) Output low voltage, all standard output and I/O pins, relative to applicable VSS (VSS_IO, VSS_MEM, or VSS_BB) Min Max Unit s Testing Conditions / Notes IOH = -4 mA2, -3 mA3 IOH = 4 mA2, 3 mA3 VOH1 VCC - 0.3 VCC V VOL1 VSS VSS + 0.3 V NOTES: 1. Programmable drive strengths set to 0x5 for memory and LCD programmable signals. 2. The current for the high-strength pins are MA<25:0>, MD<31:0>, nOE, nWE, nSDRAS, nSDCAS, DQM<3:0>, nSDCS<3:0>, SDCKE<1>, SDCLK<3:0>, RDnWR, nCS<5:0>, and nPWE. 3. The current for all other output and I/O pins are low strength. 5.5 Oscillator Electrical Specifications The PXA270 processor contains two oscillators: a 32.768-kHz oscillator and a 13.000-MHz oscillator. Each oscillator requires a specific crystal. 5.5.1 32.768-kHz Oscillator Specifications The 32.768-kHz oscillator is connected between the TXTAL_IN (amplifier input) and TXTAL_OUT (amplified output). Table 5-9 and Table 5-10 list the appropriate 32.768-kHz specifications. To drive the 32.768-kHz crystal pins from an external source: 1. Drive the TXTAL_IN pin with a digital signal that has low and high levels as listed in Table 5-10. Do not exceed VCC_PLL or go below VSS_PLL by more than 100 mV. The minimum slew rate is 1 volt per 1 s. The maximum current drawn from the external clock source when the clock is at its maximum positive voltage is typically 1 mA. 2. Float the TXTAL_OUT pin or drive it in complement to the TXTAL_IN pin, with the same voltage level and slew rate. Caution: The TXTAL_IN and TXTAL_OUT pins must not be driven from an external source if the PXA270 processor sleep / deep sleep DC-DC converter is enabled. Table 5-9. Typical 32.768-kHz Crystal Requirements (Sheet 1 of 2) Parameter Frequency range Frequency tolerance Frequency stability, parabolic coefficient Drive level Load capacitance (CL) Shunt capacitance (CO) Minimum -- -30 -- -- -- -- Typical 32.768 -- -- -- 12.5 0.9 Maximum -- +30 -0.04 1.0 -- -- Units kHz ppm ppm/ (C)2 uW pf pf Electrical, Mechanical, and Thermal Specification 5-9 Intel(R) PXA270 Processor Electrical Specifications Table 5-9. Typical 32.768-kHz Crystal Requirements (Sheet 2 of 2) Parameter Motional capacitance (CI) Equivalent series resistance (R S) Insulation resistance at 100 V DC Aging, at operating temperature per year Minimum -- -- 100 -- Typical 2.1 18 -- -- Maximum -- 35 -- 3.0 Units fF k M ppm 5-10 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Electrical Specifications Table 5-10. Typical External 32.768-kHz Oscillator Requirements Symbol Description Min Typical Max Units Amplifier Specifications VIH_X VIL_X IIN_XT CIN_XT tS_XT Input high voltage, TXTAL_IN Input low voltage, TXTAL_IN Input leakage, TXTAL_IN Input capacitance, TXTAL_IN/ TXTAL_OUT Stabilization time 0.99 -0.10 -- -- -- 1.10 0.00 -- 18 -- 1.21 0.10 1 25 10 V V A pf s Board Specifications RP_XT CP_XT COP_XT Parasitic resistance, TXTAL_IN/ TXTAL_OUT to any node Parasitic capacitance, TXTAL_IN/ TXTAL_OUT, total Parasitic shunt capacitance, TXTAL_IN to TXTAL_OUT 20 -- -- -- -- -- -- 5 0.4 M pf pf 5.5.2 13.000-MHz Oscillator Specifications The 13.000-MHz oscillator is connected between the PXTAL_IN (amplifier input) and PXTAL_OUT (amplified output). Table 5-11 and Table 5-12 list the 13.000-MHz specifications. To drive the 13.000-MHz crystal pins from an external source: 1. Drive the PXTAL_IN pin with a digital signal with low and high levels as listed in Table 5-12. Do not exceed VCC_PLL or go below VSS_PLL by more than 100 mV. The minimum slew rate is 1 volt / 1 ns. The maximum current drawn from the external clock source when the clock is at its maximum positive voltage typically is 1 mA. 2. Float the PXTAL_OUT pin or drive it in complement to the PXTAL_IN pin, with the same voltage level, slew rate, and input current restrictions. Caution: The PXTAL_IN and PXTAL_OUT pins must not be driven from an external source if the PXA270 processor sleep / deep sleep DC-DC converter is enabled. Table 5-11. Typical 13.000-MHz Crystal Requirements Parameter Frequency range Frequency tolerance at 25C Oscillation mode Maximum change over temperature range Drive level Load capacitance (CL) Maximum series resistance (RS ) Aging per year, at operating temperature Minimum 12.997 -50 -- -50 -- -- -- -- Typical 13.000 -- Fnd -- 10 10 50 -- Maximum 13.002 +50 -- +50 100 -- -- 5.0 Units MHz ppm -- ppm uW pf ppm Electrical, Mechanical, and Thermal Specification 5-11 Intel(R) PXA270 Processor Electrical Specifications Table 5-12. Typical External 13.000-MHz Oscillator Requirements Symbol Description Min Typical Max Units Amplifier Specifications VIH_X VIL_X IIN_XP CIN_XP tS_XP Input high voltage, PXTAL_IN Input low voltage, PXTAL_IN Input leakage, PXTAL_IN Input capacitance, PXTAL_IN/PXTAL_OUT Stabilization time 0.99 -0.10 -- -- -- 1.10 0.00 -- 40 -- 1.21 0.10 10 50 67.8 V V A pf ms Board Specifications RP_XP CP_XP COP_XP Parasitic resistance, PXTAL_IN/PXTAL_OUT to any node Parasitic capacitance, PXTAL_IN/PXTAL_OUT, total Parasitic shunt capacitance, PXTAL_IN to PXTAL_OUT 20 -- -- -- -- -- -- 5 0.4 M pf pf 5.6 CLK_PIO and CLK_TOUT Specifications CLK_PIO can be used to drive a buffered version of the PXTAL_IN oscillator input or can be used as a clock input alternative to PXTAL_IN. Refer to Table 5-13 for CLK_PIO specifications. A buffered and inverted version of the TXTAL_IN oscillator output is driven out on CLK_TOUT. Refer to Table 5-14 for CLK_TOUT specifications. Note: CLK_TOUT and CLK_PIO are only available when software sets the OSCC[PIO_EN] and OSCC[TOUT_EN] bits. Table 5-13. CLK_PIO Specifications Parameter Frequency Frequency Accuracy (derived from 13 MHz crystal) Symmetry/Duty Cycle variation Jitter Load capacitance (CL) Rise and Fall time (Tr & Tf) Specifications 13 MHz +/-200ppm 30/70 to 70/30% at VCC +/-20pS max 50pf max 15nS max with 50pF load Table 5-14. CLK_TOUT Specifications (Sheet 1 of 2) Parameter Frequency Frequency Accuracy (derived from 32 kHz crystal) Symmetry/Duty Cycle variation Specifications 32KHz +/-200ppm 30/70 to 70/30% at VCC 5-12 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Electrical Specifications Table 5-14. CLK_TOUT Specifications (Sheet 2 of 2) Parameter Jitter Load capacitance (CL) Rise and Fall time (Tr & Tf) Specifications +/-20pS max 50pf max 15nS max with 50pF load 5.7 48 MHz Output Specifications Software may configure GPIO<11> or GPIO<12> alternate functions to enable the 48-MHz clock output. The 48-MHz output clock is a divided-down output generated from the 312-MHz peripheral PLL. Refer to Table 5-15 for the 48-MHz output specifications. Refer to Section 3 of this document for GPIO alternate functions in the pin usage table. Table 5-15. 48 MHz Output Specifications Parameter Frequency (derived from 13 MHz crystal) Frequency Accuracy (derived from 13 MHz crystal) Symmetry/Duty Cycle variation Jitter Load capacitance (CL) Rise and Fall time (Tr & Tf) Specifications 48 MHz +/-200ppm (maximum) 30/70 to 70/30% at VCC +/-20pS max 50pf max 15nS max with 50pF load Electrical, Mechanical, and Thermal Specification 5-13 Intel(R) PXA270 Processor Electrical Specifications 5-14 Electrical, Mechanical, and Thermal Specification AC Timing Specifications 6 A pin's alternating-current (AC) characteristics include input and output capacitance. These factors determine the loading for external drivers and other load analyses. The AC characteristics also include a derating factor, which indicates how much the AC timings might vary with different loads. Note: The timing diagrams in this chapter show bursts that start at 0 and proceed to 3 or 7. However, the least significant address (0) is not always received first during a burst transfer, because the Intel(R) PXA270 processor requests the critical word first during burst accesses. Table 6-1 shows the AC operating conditions for the high- and low-strength input, output, and I/O pins. All AC specification values are valid for the device's entire temperature range. Table 6-1. Standard Input, Output, and I/O-Pin AC Operating Conditions Symbol CIN COUT_H tdF_H Description Input capacitance, all standard input and I/O pins Output capacitance, all standard highstrength output and I/O pins Output derating, falling edge on all standard, high-strength output and I/O pins, from 50-pf load. Output derating, rising edge on all standard, high-strength output and I/O pins, from 50-pf load. Output capacitance, all standard lowstrength output and I/O pins Output derating, falling edge on all standard, low-strength output and I/O pins, from 50-pf load. Output derating, rising edge on all standard, low-strength output and I/O pins, from 50-pf load. Min -- 20 -- Typical -- -- TBD Max 10 50 -- Units pf pf ns/pf tdR_H COUT_L tdF_L -- 20 -- TBD -- TBD -- 50 -- ns/pf pf ns/pf tdR_L -- TBD -- ns/pf 6.1 AC Test Load Specifications Figure 6-1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers use IBIS or other simulation tools to correlate the timing reference load to system environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). Electrical, Mechanical, and Thermal Specification 6-1 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-1. AC Test Load I/O = 50 50pf 6.2 Reset and Power Manager Timing Specifications The processor asserts the nRESET_OUT pin in one of several different modes: * * * * * * Power-on reset Hardware reset Watchdog reset GPIO reset Sleep mode Deep-sleep mode The following sections give the timing and specifications for entry into and exit from these modes. 6.2.1 Power-On Timing Specifications Power-on reset begins when a power supply is detected on the backup battery pin, VCC_BATT, after the processor has been powered off. A power-on reset is equivalent to a hardware reset, in that all units are reset to the same known state as with a hardware reset. A power-on reset is a complete and total reset that occurs only at initial power on. The external power-supply system must enable the power supplies for the processor in a specific sequence to ensure proper operation. Figure 6-2 shows the timing diagram for a power-on reset sequence. Table 6-2 details the timing. The sequence for power-on reset is as follows: 1. VCC_BATT is established, then nRESET should be de-asserted to initiate power-on reset. 2. PWR_OUT is asserted. The processor asserts nRESET_OUT. 3. The external power-control subsystem de-asserts nBATT_FAULT to signal that the main battery is connected and not discharged. 4. The processor asserts the SYS_EN signal to enable the power supplies VCC_IO, VCC_MEM, VCC_BB, VCC_USB, and VCC_LCD. VCC_USIM can be established at this time also but can be independently controlled through its own control signals. VCC_IO must be established first. The other supplies can turn on in any order, but they must all be established within 125 milliseconds of the assertion of SYS_EN. 6-2 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications 5. The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE, VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be established within 125 milliseconds of the assertion of PWR_EN. 6. The external power-control subsystem de-asserts nVDD_FAULT to signal that all system power supplies have been properly established. 7. The processor de-asserts nRESET_OUT and enters run mode, executing code from the reset vector. Note: nBATT_FAULT must be high before nRESET is de-asserted. Otherwise, the processor does not begin the power-on sequencing event. nVDD_FAULT is sampled only when the SYS_DEL and PWR_DEL timers have expired. Refer to the Intel(R) PXA27x Processor Family Developer's Manual, "Initial Power On" and "Deep-Sleep Exit States" for a state diagram. Figure 6-2. Power On Reset Timing t1 VCC_BATT nBATT_FAULT nRESET SYS_EN VCC_USB, VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USIM PWR_EN VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT t2 t3 t5 tbramp tsysramp tpwrramp t4 Table 6-2. Power-On Timing Specifications(OSCC[CRI] = 0) (Sheet 1 of 2) Symbol t1 t2 t3 t4 t5 tbramp Description Delay from VCC_BATT assertion to nRESET de-assertion Delay from nRESET de-assertion to SYS_EN assertion Delay from SYS_EN assertion to PWR_EN assertion Power supply stabilization time (time to the de-assertion of nVDD_FAULT after the assertion of PWR_EN) Delay from the assertion of PWR_EN to the de-assertion of nRESET_OUT VCC_BATT power-on Ramp Rate Min 10 -- -- -- -- -- Typical -- 101 125 -- 125 10 Max -- -- -- 120 -- 12 Units ms ms ms ms ms mV/uS Electrical, Mechanical, and Thermal Specification 6-3 Intel(R) PXA270 Processor AC Timing Specifications Table 6-2. Power-On Timing Specifications(OSCC[CRI] = 0) (Sheet 2 of 2) Symbol tsysramp Description Power-on Ramp Rate for all external high -voltage power domains Power-on Ramp Rate for all external low -voltage power domains (including dynamic voltage changes on VCC_CORE) Min -- Typical 10 Max 12 Units mV/uS tpwrramp -- 10 12 mV/uS NOTES: 1. If the OSCC[CRI] =1 then the delay from nRESET de-assertion to SYS_EN assertion is 3000mS NOTE: This long delay is attributed to the fact that when the CRI bit is read as 1, (which indicates that the CLK_REQ pin was floated during a hardware or power-on reset) the processor oscillator is supplied externally, which then forces the system to wait for the 32 kHz oscillator and the 13 MHz oscillator to stabilize. 6.2.2 Hardware Reset Timing The timing sequences shown in Figure 6-3 for hardware reset and the specifications in Table 6-3 and Table 6-4 assume stable power supplies at the assertion of nRESET. Follow the timings indicated in Section 6.2.1 if the power supplies are unstable. Figure 6-3. Hardware Reset Timing t7 nRESET t6 nRESET_OUT t8 NOTE: nBATT_FAULT and nVDD_FAULT must be deasserted during the reset sequence. Table 6-3. Hardware Reset Timing Specifications (OSCC[CRI] = 0) Symbol t6 t7 t8 Description Delay between nRESET asserted and nRESET_OUT asserted Assertion time of nRESET Delay between nRESET de-asserted and nRESET_OUT de-asserted Min -- 6 256 Typical < 100 ns -- -- Max 10 -- 265 Units ms ms ms 6-4 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Table 6-4. Hardware Reset Timing Specifications (OSCC[CRI] = 1) Symbol t6 t7 t8 Description Delay between nRESET asserted and nRESET_OUT asserted Assertion time of nRESET Delay between nRESET de-asserted and nRESET_OUT de-asserted Min -- 6 2256 Typical < 100 ns -- -- Max 10 -- 3265 Units ms ms ms 6.2.3 Watchdog Reset Timing Watchdog reset is generated internally and therefore has no external pin dependencies. The SYS_EN and PWR_EN power signals de-assert and the nRESET_OUT pin asserts during watchdog reset. The timing is similar to that for power-on reset -- see Figure 6-2 for details. 6.2.4 GPIO Reset Timing GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies based on the selected clock frequency. If the clocks and power manager is in a frequency-change sequence when GPIO reset is asserted (see Section 5.5.1, "32.768-kHz Oscillator Specifications" on page 5-9.), then Figure 6-4 shows the timing of GPIO reset, and Table 6-5 shows the GPIO reset timing specifications. Note: When bit GPROD is set in the Power Manager General Configuration register, nRESET_OUT is not asserted during GPIO reset. For register details, see the "Clocks and Power Manager" chapter in the Intel(R) PXA27x Processor Family Developer's Manual. Figure 6-4. GPIO Reset Timing tA_GPIO<1> GP[1] nRESET_OUT tDHW_OUT nCS0 tDHW_OUT_A tCS0 Electrical, Mechanical, and Thermal Specification 6-5 Intel(R) PXA270 Processor AC Timing Specifications Table 6-5. GPIO Reset Timing Specifications Symbol tA_GPIO<1> tDHW_OUT_A Description Minimum assert time of GPIO<1>1 in 13.000-MHz input clock cycles Delay between GPIO<1> asserted and nRESET_OUT asserted in 13.000-MHz input clock cycles Delay between nRESET_OUT asserted and nRESET_OUT de-asserted, run or turbo mode 2 Delay between nRESET_OUT asserted and nRESET_OUT de-asserted, during frequency change sequence 3 Delay between nRESET_OUT deassertion and nCS0 assertion Min 44 64 Typical -- -- Max -- 8 Units cycles cycles tDHW_OUT 230 -- -- nsec tDHW_OUT_F tCS05 5 1000 -- -- 380 -- s ns NOTES: 1. GPIO<1> is not recognized as a reset source again until configured to do so in software. Software must check the state of GPIO<1> before configuring as a reset to ensure that no spurious reset is generated. For details, see the "Clocks and Power Manager" chapter in the Intel(R) PXA27x Processor Family Developer's Manual. 2. Time is 512*N processor clock cycles plus up to 4 cycles of the 13.000-MHz input clock. 3. Time during the frequency-change sequence depends on the state of the PLL lock detector at the assertion of GPIO reset. The lock detector has a maximum time of 350 s plus synchronization. 4. In standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power mode. 5. The tCS0 specification is also applicable to Power-On reset, Hardware reset, Watchdog reset and DeepSleep/Sleep mode exit. 6.2.5 Sleep Mode Timing Sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals. Figure 6-5 and Table 6-6 show the required timing parameters for sleep mode. Note: When bit SL_ROD is set in the Power Manager Sleep Configuration register, nRESET_OUT, is not asserted during sleep mode. See the "Clocks and Power Manager" chapter in the Intel(R) PXA27x Processor Family Developer's Manual for register details. 6-6 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-5. Sleep Mode Timing Intel(R) PXA27x State: Wakeup Event SYS_EN VCC_USB, VCC_IO, VCC_BB,VCC_MEM, VCC_LCD, VCC_USIM PWR_EN VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT (High) (Enabled) Tentry Tpwrdelay SLEEP (ENTRY) SLEEP SLEEP (EXIT) Texit NORMAL Table 6-6. Sleep-Mode Timing Specifications Symbol tentry5 texit tpwrdelay Description Delay between MCR sleep command issue to de-assertion of PWR_EN Delay between wakeup event and run mode Delay between assertion of PWR_EN to PLL enable2 Min 0.56 0.50 0 Typical -- -- -- Max3 2.51 136.652,4 125 Units msec msec msec NOTES: 1. -1mS if not using DC2DC and -0.94mS if any internal SRAM banks are not powered 2. 0.15ms less time if exiting from sleep mode to 13M mode 3. Add 0.1ms if the wake up event is external 4. Oscillator start/crystal stable times are programmable (300uS-11mS) NOTE: 5ms is user programmable using the OSCC[OSD] bit. The remaining 6ms is an internal timer which counts until the oscillator is stable. (Typical stabilization is 500s. Maximum can be upto 5ms) 5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode 6.2.6 Deep-Sleep Mode Timing Deep-sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals. Figure 6-6 and Table 6-7 show the required timing parameters for sleep mode. The timing specifications listed are for software-invoked (not battery or VDD fault) deep-sleep entry, unless specified. Electrical, Mechanical, and Thermal Specification 6-7 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-6. Deep-Sleep-Mode Timing Intel(R) PXA27x State: Wakeup Event SYS_EN VCC_USB, VCC_IO, VCC_BB, VCC_MEM, VCC_LCD, VCC_USIM PWR_EN VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT Deep-Sleep Command Tdentry DEEP SLEEP (ENTRY) Tenable DEEP SLEEP DEEP SLEEP (EXIT) Tdexit NORMAL Tdsys_delay Tdpwr_delay Table 6-7. Deep-Sleep Mode Timing Specifications Symbol tdentry 5 tenable tdexit tdsysdelay tdpwrdelay Description Delay between deep-sleep command issue to de-assertion of SYS_EN Delay between de-assertion of PWR_EN and SYS_EN Delay between wakeup event and run mode Delay between assertion of SYS_EN to PWR_EN2 Delay between assertion of PWR_EN to PLL enable2 Min 0.66 -- 0.60 0 0 Typical -- 30 -- -- -- Max3 1.661 -- 261.75 2,4 125 125 Units msec usec msec msec msec NOTE: Timing specifications for nBATT_FAULT and/or nVDD_FAULT asserted deep-sleep mode entry are below: Delay between nBATT_FAULT or nVDD_FAULT assertion (during all modes of operation including sleep mode) and deep-sleep mode entry6(The de-assertion of SYS_EN defines when the processor is in deep-sleep mode) Fault assert 0.33 -- 1.56 msec NOTES: 1. -1ms if not using DC2DC 2. 0.15ms less time if exiting from deep-sleep mode to 13M mode 3. Add 0.1ms if the wake up event is external 4. Oscillator start/crystal stable times are programmable (300uS-11mS) NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which counts until the oscillator is stable. (Typical stabilization is 500s. Maximum can be upto 5ms) 5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode 6. Assumes PMCR[BIDAE or VIDAE] bits are set to zero (default state) - The PMCR[BIDAE or VIDAE] bits are only read by the processor if nBATT_FAULT or nVDD_FAULT signals are asserted 6-8 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications 6.2.6.1 GPIO states in Deep-Sleep mode If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, VCC_USIM) remain powered on during deep-sleep, the PGSR values are driven onto all the GPIO pins (that are configured as outputs) for a finite time period, then the pins default to the reset state (Pu/Pd) as described in Chapter 2 of this manual. This sequence occurs for either software-initiated or fault-initiated deep-sleep entry. Note: GPIOs<0,1,3,4,9,10> never float. They are powered from VCC_BATT so when the system and the core power domains are removed (controlled by SYS_EN and PWR_EN), the Pu/Pd resistors remain enabled due to VCC_BATT remaining on. The delay between the initiation of deep-sleep mode and enabling the GPIO Pu/Pd states is system dependant because the processor is performing an unpredictable workload and requires an unknown amount of time to complete current processes. Refer to the deep-sleep mode, "Clocks and Power" section of the Intel(R) PXA27x Processor Family Developers Manual for a description on deep-sleep mode entry sequence. Table 6-8 shows the time period that the GPIO pullup/pulldowns are enabled. Listed below are the regulators and converter naming conventions: L1 = Sleep/Deep-Sleep Linear Regulator L2 = High-Current Linear Regulator DC2DC = Sleep/Deep-Sleep DC-DC Converter Table 6-8. GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode Description Duration of the GPIO Pu/Pd states being enabled and the de-assertion of PWR_EN L2 0.1 L1 0.13 DC2DC 1.13 Units msec Note: If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, VCC_USIM) are powered off during deep-sleep mode, the GPIOs behave the same as described above; however, they float after the supplies are removed. Electrical, Mechanical, and Thermal Specification 6-9 Intel(R) PXA270 Processor AC Timing Specifications 6.2.7 Standby-Mode Timing Symbol -- -- -- -- Table 6-9. Standby-Mode Timing Specifications Description 13M mode to standby mode entry Standby mode exit to 13M mode 1 1 Min -- 0.28 -- 0.43 Typical 0.34 -- 0.34 -- Max -- 11.28 -- 11.43 2 2 Units msec msec msec msec Run mode to standby mode entry Standby mode exit to run mode NOTES: 1. The 13M oscillator is programmable 2. Add 0.1ms if the wake up event is external 6.2.8 Idle-Mode Timing Table 6-10. Idle-Mode Timing Specifications Symbol -- -- -- -- Description 13M mode to deep idle mode entry Deep idle mode exit to 13M mode Run mode to idle run mode entry Idle run mode exit to run mode Min -- -- -- -- Typical 1 1 1 1 Max -- -- -- -- Units s s s s 6.2.9 Frequency-Change Timing Table 6-11. Frequency-Change Timing Specifications Symbol -- -- -- -- Description Delay between MCR command to frequency change sequence completion Delay to change between turbo, halfturbo and run modes Delay to enter 13M mode from any Run mode 3 Delay to exit 13M mode to any Run mode Min -- -- -- -- Typical 1501 12 1 24 Max -- -- -- -- Units s s s s NOTES: 1. Any change to the CCCR[2N or L] bits followed by a write to CLFCFG[F] to initiate a frequency change sequence, results in a PLL restart 2. Changing between turbo, half-turbo and run modes does not require a PLL restart 3. Software can only change into 13M mode from any run mode 4. Assuming software uses the PLL early enable feature (CCCR[PLL_EARLY_EN] prior to a frequency change sequence 6-10 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications 6.2.10 Voltage-Change Timing The PWR I2C uses the regular I2C protocol. The PWR I2C is clocked at 40 kHz (160 kHz fastmode operation is supported). Software controls the time required for initiating the voltage change sequence through completion. The voltage-change timing is a product of the number of commands issued plus the number of software-programmed delays. Table 6-12 shows the timing of a 1 byte command issued to the power manager IC. Set the I2C programmable output ramp rate with a default/reset ramp rate of 10mV/s (refer to VCC_CORE ramp rate specification in the Electrical Section) to support VCC_CORE dynamic voltage management. Table 6-12. Voltage-Change Timing Specification for a 1-Byte Command Symbol -- Description Delay between voltage change sequence start1 to command received by PMIC Min -- Typical 18 Max -- Units cycles2 NOTES: 1. Write 1 to PWRMODE[VC] 2. 40 kHz cycles 6.3 GPIO Timing Specifications Table 6-13 shows the general-purpose I/O (GPIO) AC timing specifications. Table 6-13. GPIO Timing Specifications Symbol taGPIO1 taGPIOLP2 tdGPIO1 tdGPIOLP2 tdiGPIO3 tdiGPIOLP4 Parameter Assertion time required to detect GPIO edge Assertion time required to detect GPIO low-power edge De-assertion time required to detect GPIO edge De-assertion time required to detect GPIO low-power edge Time required for a GPIO edge to be detected internally Time required for a GPIO lowpower edge to be detected internally Min 154 62.5 154 62.5 231 93.75 Max -- -- -- -- -- -- Units ns s ns s ns s Notes run, idle, or sense power modes standby, sleep, or deep-sleep power modes run, idle, or sense power modes standby, sleep, or deep-sleep power modes run, idle, or sense power modes standby, sleep, or deep-sleep power modes NOTES: 1. Period equal to two 13-MHz cycles 2. Period equal to two 32-kHz cycles 3. Period equal to three 13-MHz cycles 4. Period equal to three 32-kHz cycles Note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally (2 cycles for assertion (note 2) and 1 additional cycle for detection). Electrical, Mechanical, and Thermal Specification 6-11 Intel(R) PXA270 Processor AC Timing Specifications 6.4 Memory and Expansion-Card Timing Specifications Interfaces with the following memories must observe the AC timing requirements given in the following subsections: * * * * * * * Note: Section 6.4.1, "Internal SRAM Read/Write Timing Specifications" Section 6.4.2, "SDRAM Parameters and Timing Diagrams" Section 6.4.3, "ROM Parameters and Timing Diagrams" Section 6.4.4, "Flash Memory Parameters and Timing Diagrams" Section 6.4.5, "SRAM Parameters and Timing Diagrams" Section 6.4.6, "Variable-Latency I/O Parameters and Timing Diagrams" Section 6.4.7, "Expansion-Card Interface Parameters and Timing Diagrams" The diagrams in this section use the following conventions: * Input signals to the processor are represented using dashed waveforms. * Outputs and bidirectional signals are represented using solid waveforms. * Fixed parameters are shown using double arrows in grey (black and white print) or green (color print). * Programmable parameters are shown using bold single arrows. * The processor register that is used to change a specific timing is given in the corresponding timing table. 6.4.1 Internal SRAM Read/Write Timing Specifications Symbols tsramRD tsramWR Table 6-14. SRAM Read/Write AC Specification Parameters 4-beat read transfer 4-beat write transfer MIN -- -- TYP 9 7 MAX -- -- Units system bus clocks system bus clocks 6.4.2 SDRAM Parameters and Timing Diagrams Table 6-15 shows the timing parameters used in Figure 6-7. Also see Section 6.4.3 and Figure 6-11 for additional SDRAM bus tenure information. See Figure 6-10 for SDRAM fly-by bus tenures. 6-12 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Table 6-15. SDRAM Interface AC Specifications (Sheet 1 of 2) Symbols Parameters Units MAX 76.9 1 ns SDCLK Notes 1, 2 -- -- 6 6 6 6 6 -- -- -- VCC_MEM = 1.8V +20% / -5%3 MIN TYP -- -- VCC_MEM = 2.5V +/- 10%4 MIN 9.6 1 VCC_MEM = 3.3V +/- 10%5 MAX 76.9 1 MAX 76.9 1 TYP -- -- MIN 9.6 1 TYP -- -- tsdCLK tsdCMD SDCLK1, SDCLK2 period nSDCAS, nSDRAS, nWE, nSDCS assert time nSDCAS to nSDCAS assert time nSDRAS to nSDCAS assert time nSDRAS Pre charge nSDRAS to nSDCAS delay nSDRAS active time nSDRAS cycle time write recovery time (time from last data in the PRECHARGE) MA<24:10>, MD<31:0>, DQM<3:0>, nSDCS<3:0>, nSDRAS, nSDCAS, nWE, nOE, SDCKE1, RDnWR output setup time to SDCLK<2:1> rise MA<24:10>, MD<31:0>, DQM<3:0>, nSDCS<3:0>, nSDRAS, nSDCAS, nWE, nOE, SDCKE1, RDnWR output hold time from SDCLK<2:1> rise 9.6 1 tsdCAS 2 -- MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] -- -- 2 -- MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] -- -- 2 -- MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] MDCNFG [DTCx] -- -- SDCLK tsdRCD tsdRP tsdCL tsdRAS tsdRC 1 2 2 3 4 3 3 3 7 11 1 2 2 3 4 3 3 3 7 11 1 2 2 3 4 3 3 3 7 11 SDCLK SDCLK SDCLK SDCLK SDCLK tsdWR 2 2 2 2 2 2 SDCLK tsdSDOS 2.5 -- -- 2.5 -- -- -- -- ns tsdSDOH 1.5 -- -- 1.5 -- -- -- -- ns VCC_CORE = 0.85 V +/- 10%, with 1.71 V<= VCC_MEM <= 3.63 V VCC_CORE = 1.1 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V VCC_CORE = 1.3 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V Electrical, Mechanical, and Thermal Specification 6-13 Intel(R) PXA270 Processor AC Timing Specifications Table 6-15. SDRAM Interface AC Specifications (Sheet 2 of 2) Symbols Parameters Units MAX Notes -- -- VCC_MEM = 1.8V +20% / -5%3 MIN TYP MAX MIN VCC_MEM = 2.5V +/- 10%4 TYP MAX MIN VCC_MEM = 3.3V +/- 10%5 TYP tsdSDIS MD<31:0> read data input setup time from SDCLK<2:1> rise MD<31:0> read data input hold time from SDCLK<2:1> rise 3.0 -- -- 3.0 -- -- 0.5 -- -- ns tsdSDIH 2.0 -- -- 2.0 -- -- 1.8 -- -- ns NOTES: 1. SDCLK for SDRAM slowest period is accomplished by divide-by-2 of the 26-MHz CLK_MEM. The fastest possible SDCLK is accomplished by configuring CLK_MEM at 104 MHz and not setting MDREFR[KxDB2]. 2. SDCLK1 and SDCLK2 frequencies are configured to be CLK_MEM frequency divided by 1 or 2, depending on the bit fields MDREFR[K1DB2] and MDREFR[K2DB2] settings. 3. These numbers are for VCC_MEM = 1.8 V +20% / -5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK<2:1> divide-by-2 and divide-by-4 register bits MDREFR[KxDB2] clear. 4. These numbers are for VCC_MEM = 2.5 V +/- 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divideby-2 and divide-by-4 register bit MDREFR[KxDB2] clear. 5. These numbers are for VCC_MEM = 3.3 V +/- 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divideby-2 and divide-by-4 register bit MDREFR[KxDB2] clear. 6. Refer to the "Memory Controller" chapter in the Intel(R) PXA27x Processor Family Developer's Manual for register configuration. 6-14 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-7. SDRAM Timing tsdCLK SDCLK<1> SDCKE<1> tsdRC tsdCL tsdRP tsdCMD command nop act nSDCS<0> tsdRAS nSDRAS tsdRCD nSDCAS nWE tsdSDIS tsdIH MD<31:0> read tsdSDOS tsdSDOH tWR MD<31:0> write DQM<3:0> RDnWR 0b0000 nop read nop pre nop act nop write tsdCMD nop pre nop 0 1 2 3 mask data values Electrical, Mechanical, and Thermal Specification 6-15 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-8. SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing SDCLK<1> SDCKE<1> command nSDCS<0> nSDCS<1> nSDRAS nSDCAS MA<24:10> nWE MD<31:0> (read) MD<31:0> (write) DQM<3:0> RDnWR 0b0000 rd0_0 rd0_1 rd0_2 rd0_3 wd1_0 wd1_1 wd1_2 wd1_3 read(0) pre(1) nop act(1) nop write(1) nop col bank row col 0 1 2 3 mask data bytes NOTES: 1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk), MDCNFG[STACK] = 0b00 2. See the SDRAM timing diagram. 6-16 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-9. SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing SDCLK<1> SDCKE<1> command nSDCS<0> nSDRAS nSDCAS MA<24:10> nWE MD<31:0> DQM<3:0> RDnWR NOTES: 1. MDCNFG[DTC] = 0b01 (CL = 2, tRP = 2 clks) 2. See the SDRAM timing diagram. wd0_0 wd0_1 wd0_2 wd0_3 wd0_4 wd0_5 wd0_6 wd0_7 mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7 mask data bytes col col nop write(0) nop write(0) nop Electrical, Mechanical, and Thermal Specification 6-17 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-10. SDRAM Fly-by DMA Timing latch data rd3 latch data rd2 latch data rd1 latch data rd0 SDCLK<1> latch DVAL[1] asserted drive data wd0 drive data wd1 drive data wd2 drive data wd3 SDCLK<2> SDCKE<1> command nSDCS<0> nSDCS<2> nSDRAS nSDCAS MA<24:10> nWE MD<31:0> DQM<3:0> RDnWR DVAL<0> DVAL<1> rd0 rd1 rd2 rd3 wd0 wd1 wd2 wd3 0b0000 mask0 mask1 mask2 mask3 read pre nop act nop write nop col bank row col mask data bytes Latch data on rising edge of SDCLK<1> when DVAL<0> is asserted. Using DVAL<1> driven two clocks early, drive data on rising edge of SDCLK<2>. NOTES: 1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk) 2. See the SDRAM timing diagram. 6.4.3 ROM Parameters and Timing Diagrams Table 6-16 lists the timings for ROM reads. See Figure 6-11, Figure 6-12, Figure 6-13, and Figure 6-14 for timings diagrams representing burst and non-burst ROM reads. Note: Table 6-16 lists programmable register items. See the "Memory Controller" chapter in the Intel(R) PXA27x Processor Family Developer's Manual for register configurations for more information on these items. Table 6-16. ROM AC Specification (Sheet 1 of 2) Symbols tromAS tromCES tromCEH tromDSOH Parameters Address setup to nCS assert nCS setup to nOE asserted nCS hold from nOE de-asserted MD setup to address valid MIN 1 -- -- 1.5 TYP -- -- -- -- MAX 1 0 0 -- Units clk_mem clk_mem clk_mem clk_mem Notes -- -- -- -- 6-18 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Table 6-16. ROM AC Specification (Sheet 2 of 2) Symbols tromDOH tromAVDVF tromAVDVS tflashAVDVS tromCD Parameters MD hold from address valid Address valid to data valid for the first read access Address valid to data valid for subsequent reads of non-burst devices Address valid to data valid for subsequent reads of burst devices nCS de-asserted after a read of next nCS or nSDCS asserted (minimum) MIN 0 2 1 1 1 TYP -- MSCx[RDF]+2 MSCx[RDF]+1 MSCx[RDN]+1 MSCx[RRR]*2+ 1 MAX -- 32 31 31 15 Units clk_mem clk_mem clk_mem clk_mem clk_mem Notes -- -- -- -- -- Numbers shown as integer multiples of the clk_mem period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). For more information, refer to the "Memory Control" chapter in the Intel(R) PXA27x Processor Family Developer's Manual. Electrical, Mechanical, and Thermal Specification 6-19 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-11. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing CLK_MEM tromAS nCS<0> tromAVDVS 2 tromAVDVS tromAVDVS 3 MA<25:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') nADV(nSDCAS) 0 tromAVDVF 1 0b00 0b00 / 0b01 / 0b10 / 0b11 tromCES nOE nWE RDnWR tromDOH tromDSOH tromCEH tromDOH tromDSOH MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') tromDOH tromDSOH tromDOH tromDSOH 0b00 corresponding mask value tromCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 4, MSC0[RRR0] = 1 6-20 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-12. 32-Bit Burst-of-Eight ROM or Flash Read Timing CLK_MEM nCS<0> tAS MA<25:5> tromAVDVF tromAVDVS 1 2 3 4 0b00 0b00 / 0b01 / 0b10 / 0b11 MA<4:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') nADV(nSDCAS) 0 5 6 7 tCES nOE nWE RDnWR tDOH tDSOH MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx NOTE: MSC0[RDF0] = 4, MSC0[RDN0] = 1, MSC0[RRR0] = 1 tCEH 0b0000 corresponding mask value tromCD Electrical, Mechanical, and Thermal Specification 6-21 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-13. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing CLK_MEM nCS<0> tromAS MA<25:4> MA<3> tromAVDVF tromAVDVS tromAVDVF MA<2:1> MA<0>(SA1110x='0') MA<0>(SA1110x='1') nADV(nSDCAS) tromCES nOE nWE RDnWR tromDOH tromDSOH MD<15:0> DQM<1:0>(SA1110x='0') DQM<1:0>(SA1110x='1') nCSx or nSDCSx NOTE: MSC0[RDF0] = 4, MSC0[RDN0] = 1, MSC0[RRR0] = 0 address tromAVDVS 0 1 2 3 0b0 0b0 / 0b1 0 1 2 3 tromCEH tromDOH tromDSOH 0b00 0b00 or 0b10/0b01 tromCD 6-22 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-14. 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing CLK_MEM tromCD nCS<0> addr tromCD tromCD tromAS 0 MA<25:1> MA<0>(SA1110x='0') MA<0>(SA1110x='1') nADV(nSDCAS) addr + 1 tromAS addr 0 0/1 tromAS addr 0 0/1 addr tromAS 0 addr + 1 0/1 tromAVDVF tromAVDVS 0/1 tflashAVDVS tromAVDVF tromAVDVF tromAVDVF tromCES nOE nWE RDnWR tromCEH tromCES tromCES tromCES tromDSOH tromDOH tromDOH tromDSOH MD<15:0> DQM<1:0>(SA1110x='0') DQM<1:0>(SA1110x='1') 0b00 mask 0b00 mask 0b00 mask tromDOH tromDSOH tromDSOH tromDOH 0b00 mask tromDOH tromDSOH tromDOH tromDSOH 32-bit read Applies to: 16-bit ROM or non-burst flash 16-bit SRAM 16-bit read Applies to: 16-bit ROM or non-burst flash 16-bit SRAM 16-bit burst flash 8-bit read Applies to: 16-bit ROM or non-burst flash 16-bit SRAM 16-bit burst flash 32-bit Read Applies to: 16-bit Burst Flash NOTE: MSC0[RDF0] = 2, MSC0[RDN0] = 1, MSC0[RRR0] = 1 6.4.4 Flash Memory Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for asynchronous and synchronous flash-memory interfaces with the memory controller. 6.4.4.1 Flash Memory Read Parameters and Timing Diagrams Section 6.4.4.1.1 describes asynchronous flash reads. Section 6.4.4.1.2 describes synchronous flash reads. 6.4.4.1.1 Asynchronous Flash Read Parameters and Timing Diagrams The timings listed in Table 6-16 for ROM reads also apply to asynchronous flash reads. See Figure 6-11, Figure 6-12, Figure 6-13, and Figure 6-14 for timings diagrams representative of an asynchronous flash read. Electrical, Mechanical, and Thermal Specification 6-23 Intel(R) PXA270 Processor AC Timing Specifications 6.4.4.1.2 Synchronous Flash Read Parameters and Timing Diagrams Table 6-17 lists the timing parameters used in Figure 6-15, and, for stacked flash packages, Figure 6-16. Table 6-17. Synchronous Flash Read AC Specifications (Sheet 1 of 2) Symbols Parameters MIN TYP Divide by 12 tffCLK tffAS SDCLK0 period MA<25:0> setup to nSDCAS (as nADV) asserted nCS setup to nSDCAS (as nADV) asserted nSDCAS (as nADV) pulse width 9.6 1 -- -- 38.5 1 19. 2 1 MAX MIN TYP Divide by 23 -- -- MAX MIN TYP Divide by 44 MAX Units 76.9 2 38.5 1 -- -- 154 4 ns CLK_MEM -- tffCES tffADV 1 1 -- -- FCC - 1 (for FCC<5) FCC - 2 (for FCC>=5) 1 1 1 3 -- -- (FCC - 1) *2 (for FCC<5) (FCC - 2) *2 (for FCC>=5) -- FCC 2 3 1 7 -- -- (FCC * 4) -7 (for FCC<5) (FCC - 2) *4 (for FCC>=5) -- FCC 4 7 CLK_MEM CLK_MEM -- -- tffOS nSDCAS (as nADV) de-assertion to nOE assertion 1 13 2 26 7 52 CLK_MEM tffCEH tffDS nOE de-assertion to nCS deassertion CLK to data valid 4 2 -- FCC 4 15 8 2 8 15 16 2 16 15 CLK_MEM CLK_MEM -- 5 VCC_MEM = 1.8V +20% / -5%6 MA<25:0>, MD<31:0>, DQM<3:0>, nCS<3:0>, nSDCAS (nADV), nWE, nOE, RDnWR output setup time to SDCLK<2:1> rise MA<25:0>, MD<31:0>, DQM<3:0>, nCS<3:0>, nSDCAS (nADV), nWE, nOE, RDnWR output hold time from SDCLK<2:1> rise VCC_MEM = 2.5V +/- 10%7 VCC_MEM = 3.3V +/- 10%8 tffSDOS TBD -- -- TB D -- -- TBD -- -- ns -- tffSDOH TBD -- -- TB D -- -- TBD -- -- ns -- VCC_CORE = 0.85 V +/ - 10%, with 1.71 V<= VCC_MEM <= 3.63 V VCC_CORE = 1.1 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V VCC_CORE = 1.3 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V 6-24 Electrical, Mechanical, and Thermal Specification Notes 1 5 Intel(R) PXA270 Processor AC Timing Specifications Table 6-17. Synchronous Flash Read AC Specifications (Sheet 2 of 2) Symbols Parameters MD<31:0> read data input setup time from SDCLK<2:0> rise MD<31:0> read data input hold time from SDCLK<2:0> rise MIN TYP MAX MIN TYP MAX MIN TYP MAX Units tffSDIS TBD -- -- 0.5 -- -- 0.5 -- -- ns -- tffSDIH TBD -- -- 1.8 -- -- 1.8 -- -- ns -- NOTES: 1. SDCLK0 may be configured to be CLK_MEM divided by 1, 2 or 4. SDCLK0 for synchronous flash memory can be at the slowest, divide-by-4 of the 26-MHz CLK_MEM. The fastest possible SDCLK0 is accomplished by configuring CLK_MEM at 104 MHz and clearing the MDREFR[K0DB2] or MDREFR[K0DB4] bit fields. 2. SDCLK0 frequency equals CLK_MEM frequency (MDREFR[K0DB4] and MDREFR[K0DB2] bit fields are clear) 3. SDCLK0 frequency equals CLK_MEM/2 frequency (MDREFR[K0DB2] is set and MDREFR[K0DB4] is clear). 4. SDCLK0 frequency equals CLK_MEM/4 frequency (MDREFR[K0DB4] is set). 5. Use SXCNFG[SXCLx] to configure the value for the frequency configuration code (FCC). 6. These numbers are for VCC_MEM = 1.8 V +20% / -5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCN TRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK0 divideby-2 and divide-by-4 register bits (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period. 7. These numbers are for VCC_MEM = 2.5 V +/- 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2 and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period. 8. These numbers are for VCC_MEM = 3.3 V +/- 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2 and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period. Electrical, Mechanical, and Thermal Specification 6-25 Notes Intel(R) PXA270 Processor AC Timing Specifications Figure 6-15. Synchronous Flash Burst-of-Eight Read Timing CLK_MEM SDCLK<0> MA<19:2> MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) nCS<0> CODE CODE+1 nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) 0b0000 corresponding mask value NOTES: 1) SXCNFG[CL] = 0b100 (CL = 5, frequency code configuration = 4) 2) CODE = frequency configuration code 0b00 0b00/0b01/0b10/0b11 6-26 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-16. Synchronous Flash Stacked Burst-of-Eight Read Timing CLK_MEM SDCLK<3> MA<19:2> MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) nCS<0> CODE CODE+1 nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) 0b0000 corresponding mask value NOTE: SXCNFG[CL] = 0b100 (CL = 5, frequency code configuration = 4) SA1110CR[SXSTACK] = 0b01 0b00 0b00/0b01/0b10/0b11 Electrical, Mechanical, and Thermal Specification 6-27 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-17 indicates which clock data would be latched following the assertion of nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in the diagram indicated by different frequency configuration codes (Fcodes or FCCs) is equal to the number of SDCLK0 cycles between the READ command and the clock edge on which data is driven onto the bus. Figure 6-17. First-Access Latency Configuration Timing SDCLK<0> nCS<0> MA<19:0> nSDCAS DQM<3:0> Code 2 MD (Code = 2) Code 3 MD (Code = 3) Code 4 MD (Code = 4) Code 5 MD (Code = 5) Code 6 MD (Code = 6) Code 7 MD (Code = 7) Beat 0 Beat 0 Beat 1 Beat 0 Beat 1 Beat 2 Beat 0 Beat 1 Beat 2 Beat 3 Beat 0 Beat 1 Beat 2 Beat 3 Beat 4 Beat 0 Beat 1 Beat 2 Beat 3 Beat 4 Beat 5 0b0000 Valid Address NOTE: CODE = Frequency Configuration Code 6-28 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications The burst read example shown in Figure 6-18 represents waveforms that result when SXCNFG[SXCLx] is configured as 0b0100, representing a frequency configuration code equal to 3. The following example can help determine the appropriate setting for SXCNFG[SXCLx]. Parameters defined by the processor: * tffSDOH (max) = SDCLK<0> to CE# (nCE), ADV# (nADV), or address valid, whichever occurs last * tffSDIS (min) = Data setup to SDCLK<0> Parameters defined by flash memory: * tVLQV (min) = ADV# low to output delay * tVLCH (min) = ADV# low to clock * tCHQV (max) = SDCLK<0> to output valid Use the following equations when calculating the frequency configuration code: (1) SDCLK period = (1 / frequency) (2) n (SDCLK period) tVLQV - tVLCH - tCHQV (3) n = (tVLQV - tVLCH - tCHQV) / SDCLK period, where n = frequency configuration code rounded up to integer value (4) SDCLK period tCHQV + tffSDIS Example The timing information below is only an example. See Table 6-17 for actual synchronous AC timings. SDCLK<0> frequency = 50 MHz tVLQV = 70 ns (typical timing from synchronous flash memory) tVLCH = 10 ns (min) tCHQV = 14 ns (min) From Eq.(1): 1 / 50 (MHz) = 20 ns From Eq.(2): n(20 ns) 70 ns - 10 ns - 14 ns n(20 ns) 46 ns n = (46 / 20) ns = 2.3 ns n=3 Use Equation 4 to help verify the maximum possible frequency at which the synchronous flash memory can run with the memory controller. The following example uses Equation 4: SDCLK<0> frequency = 66 MHz tCHQV = 11 ns (max) tffSDIS = 3 ns (min) From Eq. (1): 1 / 66 (MHz) = 15.15 ns From Eq. (4): 15.15 ns 11 ns + 3 ns 15.15 ns 14 ns The results from this example indicate that the 66-MHz memory works without problems with the memory controller. Note: All AC timings must be considered to avoid timing violations in the memory-to-memory-controller interface. Electrical, Mechanical, and Thermal Specification 6-29 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-18. Synchronous Flash Burst Read Example SDCLK<0> tffSDOH nCS<0> tAVCH tffSDOH nSDCAS (ADV#) tffSDOH MA Valid Address tffSDIS tCHQV tVLQV MD Beat 0 Beat1 6.4.4.2 Flash Memory Write Parameters and Timing Diagrams Table 6-18 lists the AC specification for both burst and non-burst flash writes shown in Figure 6-19 and, for stacked flash packages, Figure 6-20. Table 6-18. Flash Memory AC Specification (Sheet 1 of 2) Symbols tflashAS tflashAH tflashASW tflashCES tflashCEH tflashWL tflashDSWH tflashDH tflashDSOH Parameters Address setup to nCS assert Address hold from nWE de-asserted Address setup to nWE asserted nCS setup to nWE asserted nCS hold from nWE de-asserted nWE asserted time MD/DQM setup to nWE de-asserted MD/DQM hold from nWE deasserted MD setup to address valid MIN 1 1 1 2 1 1 2 1 1.5 TYP -- -- -- -- -- MSCx[RDF]+1 MSCx[RDF]+2 -- -- MAX 1 1 3 2 1 31 32 1 -- Units1 clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem Notes -- -- 2 -- -- -- -- -- -- 6-30 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Table 6-18. Flash Memory AC Specification (Sheet 2 of 2) Symbols tflashDOH tflashCD Parameters MD hold from address valid nCS de-asserted after a read/write to next nCS or nSDCS asserted (minimum) MIN 0 1 TYP -- MSCx[RRR]*2 + 1 MAX -- 15 Units1 clk_mem clk_mem Notes -- -- NOTES: 1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. On the first data beat of burst transfer, the tflashASW is 3 CLK_MEM periods. On subsequent data beats, the tflashASW is 1 CLK_MEM period. Figure 6-19. 32-Bit Flash Write Timing CLK_MEM tflashCD nCS<0> MA<25:2> MA<1:0> tflashASW tflashCEH tflashCES tflashAH tflashWL nWE nOE RDnWR tflashDH tflashDSWH MD<31:0> DQM<3:0> nADV(nSDCAS) tflashCD nCSx or nSDCSx First Bus Cycle Second Bus Cycle CMD 0b0000 DATA 0b0000 tflashDH tflashDSWH tflashCES tflashAH tflashWL tflashAS command address 0b00 tflashAS data address 0b00 tflashASW tflashCEH NOTE: MSC0[RDF0] = 2, MSC0[RRR0] = 2 Electrical, Mechanical, and Thermal Specification 6-31 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-20. 32-Bit Stacked Flash Write Timing CLK_MEM tflashCD nWE MA<25:2> MA<1:0> tflashASW tflashCEH tflashCES tflashAH tflashWL nCS<0> or nCS<1> nOE RDnWR tflashDH tflashDSWH MD<31:0> DQM<3:0> nADV(nSDCAS) tflashCD nCSx First Bus Cycle Second Bus Cycle CMD 0b0000 DATA 0b0000 tflashDH tflashDSWH tflashCES tflashAH tflashWL tflashAS command address 0b00 tflashASW tflashCEH tflashAS data address 0b00 * MSC0[RDF0] = 2, MSC0[RRR0] = 2, SA1110{SXSTACK] = 00 6-32 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-21. 16-Bit Flash Write Timing CLK_MEM nCS<2> tflashAS MA<25:1> MA<0> addr 0b0 tflashCEH tflashCES tflashWL nWE nOE RDnWR tflashDH tflashDSWH MD<15:0> DQM<1:0> nADV(nSDCAS) tflashCD nCSx or nSDCSx Applies to: 16-bit Non-Burst Flash 16-bit Burst Flash NOTE: MSC1[RDN2] = 2, MSC1[RDF2] = 1, MSC1[RRR2] = 2 Bytes 1:0 0b00 6.4.5 SRAM Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for SRAM interfaces with the memory controller. 6.4.5.1 SRAM Read Parameters and Timing Diagrams The timing for a read access is identical to that for a non-burst ROM read (see Figure 6-11). The timings listed in Table 6-16 for ROM reads are also used for SRAM reads. See Figure 6-11 and Figure 6-14 for timings diagrams representing 16-bit SRAM transferring four, two, and one byte(s) during read-bus tenures. 6.4.5.2 SRAM Write Parameters and Timing Diagrams Figure 6-22 and Figure 6-23 show the timing for 32-bit and 16-bit SRAM writes. Table 6-19 lists the timings used in Figure 6-22 and Figure 6-23. Electrical, Mechanical, and Thermal Specification 6-33 Intel(R) PXA270 Processor AC Timing Specifications During writes, data pins are actively driven by the processor and are not three-stated, regardless of the states of the individual DQM signals. For SRAM writes, the DQM signals are used as byte enables. Note: Table 6-19 lists programmable register items. See the "Memory Controller"chapter in the Intel(R) PXA27x Processor Family Developer's Manual for register configurations for more information on these items. Table 6-19. SRAM Write AC Specification Symbols tsramAS tsramAH tsramASW tsramCES tsramCEH tsramWL tsramDSWH tsramDH tramCD Parameters Address setup to nCS assert Address hold from nWE de-asserted Address setup to nWE asserted nCS setup to nWE asserted nCS hold from nWE de-asserted nWE asserted time MD/DQM setup to nWE de-asserted MD/DQM hold from nWE deasserted nCS de-asserted after a read to next nCS or nSDCS asserted (minimum) MIN 1 1 1 2 1 1 2 1 1 TYP -- -- -- -- -- MSCx[RDN]+1 MSCx[RDN]+2 -- MSCx[RRR]*2+ 1 MAX 1 1 3 2 1 31 32 1 15 Units1 clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem Notes -- -- 2 -- -- -- -- -- -- NOTES: 1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. On the first data beat of burst transfer, the tsramASW is 3 CLK_MEM periods. On subsequent data beats, the tsramASW is 1 CLK_MEM period. 6-34 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-22. 32-Bit SRAM Write Timing CLK_MEM nCS<0> tsramAS 0 byte addr tsramASW tsramCESW tsramASW tsramAH tsramWL tsramWL nWE nOE RDnWR tsramDH tsramDSWH tsramDOH D1 mask1 tsramCEHW 1 byte addr 2 byte addr 3 byte addr MA<25:2> MA<1:0> tsramWL tsramAH tsramWL MD<31:0> DQM<3:0> D0 mask0 D2 mask2 D3 mask3 tsramCD nCSx or nSDCSx nADV(nSDCAS) NOTE: 4-Beat burst, MSC0[RDN0] = 2, MSC0[RRR0] = 1 Electrical, Mechanical, and Thermal Specification 6-35 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-23. 16-bit SRAM Write for 4/2/1 Byte(s) Timing CLK_MEM tsramCD nCS<2> MA<25:1> MA<0> tramAS addr '0' addr+1 '0' tramAS addr '0' tsramCEH tsramCES tsramWL tsramCES tsramWL tramAS addr '0' or '1' tsramCEH tsramCD tsramWL tsramASW tsramAH tsramCES tsramCEH tsramWL tsramWL nWE nOE RDnWR tsramDH tsramDH tsramDSWH MD<15:0> DQM<1:0> nADV(nSDCAS) tsramDSWH Bytes 1:0 Bytes 3:2 0b00 tsramDH tsramDSWH Bytes 1:0 0b00 tsramDH tsramDSWH Byte 0 OR 1 0b01 / 0b10 tsramCD nCSx or nSDCSx 32-bit Write 16-bit Write 8-bit Write NOTE: MSC1[RDF2]=1, MSC1[RDN]=2, MSC1[RRR2]=2 6.4.6 Variable-Latency I/O Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for VLIO memory interfaces with the memory controller. Table 6-20 lists the timing-information references for both the read and the write timing diagrams. Note: Table 6-20 lists programmable register items. For more information on these items, see the "Memory Controller" chapter in the Intel(R) PXA27x Processor Family Developer's Manual for register configurations. 6-36 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Table 6-20. VLIO Timing Symbols tvlioAS tvlioAH tvlioASRW0 tvlioASRWn tvlioCES tvlioCEH tvlioDSWH tvlioDH tvlioDSOH tvlioDOH tvlioRDYH tvlioRWA tvlioRWD tvlioCD Parameters Address setup to nCS asserted Address hold from nPWE/nOE deasserted Address setup to nPWE/nOE asserted (1st access) Address setup to nPWE/nOE asserted (next access(es)) nCS setup to nPWE/nOE asserted nCS hold from nPWE/nOE deasserted MD/DQM setup (minimum) to nPWE de-asserted MD/DQM hold from nPWE deasserted MD setup to address changing MD hold from address changing RDY hold from nPWE/nOE deasserted nPWE/nOE assert period between writes nPWE/nOE de-asserted period between writes nCS de-asserted after a read/write to next nCS or nSDCS asserted (minimum) MIN 1 2 3 2 2 1 5 1 1.5 0 0 4 4 1 TYP -- MSCx[RDN] -- MSCx[RDN] -- -- MSCx[RDF]+2 -- MAX2 1 30 3 30 2 1 32 1 -- -- Units1 clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem clk_mem ns ns clk_mem clk_mem clk_mem Notes -- -- -- -- -- -- -- -- -- -- -- -- 3 -- MSC[RDF]+1 + Waits MSCx[RDN*2] MSCx[RRR]*2 + 1 -- 31 + Waits 60 15 -- NOTES: 1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. Maximum values reflect the register dynamic ranges. 3. Depending on the programmed value of MSC[RDN] and the clk_mem speed, this can be a significant amount of time. Processor does not drive the data bus during this time between transfers. If the VLIO does not drive the data bus during this time between transfers, the data bus is not driven for this period of time. If MSC[RDN] is programmed to 60 (which equals 60 CLK_MEM cycles), then the data bus could potentially not be driven for 30*2 = 60 CLK_MEM cycles. 6.4.6.1 Variable Latency I/O Read Timing Figure 6-24 shows the timing for 32-bit variable-latency I/O (VLIO) memory reads. Table 6-20 lists the timing parameters used in these diagrams. Electrical, Mechanical, and Thermal Specification 6-37 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-24. 32-Bit VLIO Read Timing CLK_MEM nCS<0> MA<25:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') tvlioAS addr addr + 1 addr + 2 0b00 addr + 3 tvlioASRW0 0b00/0b01/0b10/0b11 tvlioASRWn tvlioASRWn tvlioAH tvlioAH 2 Waits tvlioASRWn tvlioAH 3 Waits tvlioAH 0 Waits 1 Wait tvlioCES nOE nPWE RDnWR tvlioCEH tvlioRWA tvlioRWA tvlioRWD tvlioRWD tvlioRWA tvlioRWD tvlioRDYH RDY RDY_sync tvlioRDYH tvlioRDYH tvlioRDYH tvlioDOH tvlioDSOH MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx tvlioDOH tvlioDSOH tvlioDOH tvlioDSOH tvlioDSOH tvlioDOH 0b0000 corresponding mask value tvlioCD NOTE: MSC0[RDF0] = 3, MSC0[RDN0 = 2, MSC0[RRR0] = 1 6.4.6.2 Variable-Latency I/O Write Timing Figure 6-25 shows the timing for 32-bit VLIO memory writes. Table 6-20 list the timing parameters used in Figure 6-25. 6-38 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-25. 32-Bit VLIO Write Timing CLK_MEM nCS<0> MA<25:2> MA<1:0> tvlioASRW0 tvlioCES 0 Waits tvlioASRWn tvlioAH 1 Wait tvlioRWD tvlioRWA nPWE nOE RDnWR tvlioRDYH RDY RDY_sync tvlioDH tvlioDSWH tvlioDSWH D1 mask1 tvlioDH tvlioDSWH D2 mask2 tvlioDH tvlioDSWH D3 mask3 tvlioCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 3, MSC0[RDN0] = 2, MSC0[RRR0] = 1 tvlioDH tvlioRDYH tvlioRDYH tvlioRDYH tvlioAS addr addr + 1 0b00 tvlioASRWn tvlioAH 2 Waits tvlioRWA tvlioRWD tvlioASRWn tvlioAH 3 Waits tvlioRWA tvlioRWD tvlioAH addr + 2 addr + 3 tvlioCEH tvlioRWA MD<31:0> DQM<3:0> D0 mask0 Electrical, Mechanical, and Thermal Specification 6-39 Intel(R) PXA270 Processor AC Timing Specifications 6.4.7 Expansion-Card Interface Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for CompactFlash* and PC Card* (expansion card) memory interfaces with the memory controller. Table 6-21 shows the timing parameters used in the timing diagrams, Figure 6-26 and Figure 6-27. Note: Table 6-21 lists programmable register items. See the "Memory Controller" chapter in the Intel(R) PXA27x Processor Family Developer's Manual for register configurations for more information on these items. Table 6-21. Expansion-Card Interface AC Specifications Symbols tcdAVCL tcdCHAI tcdDVCL tcdCHWDI tcdDVCH tcdCHRDI tcdCMD tcdILCL tcdCHIH tcdCLPS tcdPHCH Parameters Address Valid to CMD Low CMD High to Address Invalid Write Data Valid to CMD Low CMD High to Write Data Invalid Read Data Valid to CMD High CMD High to Read Data Invalid CMD Assert During Transfers nIOIS16 Low to CMD Low CMD High to nIOIS16 High CMD Low to nPWAIT Sample nPWAIT High to CMD High MIN 2 0 -- -- 2 0 -- 4 2 -- -- TYP MCx[SET] MCx[HOLD] 1 4 -- -- tcdCLPS + tcdPHCH + nPWAIT assertion -- -- x_ASST_WAIT x_ASST_HOLD MAX 127 63 -- -- -- -- -- -- -- -- -- Units CLK_MEM CLK_MEM CLK_MEM CLK_MEM CLK_MEM ns CLK_MEM CLK_MEM CLK_MEM CLK_MEM CLK_MEM Notes 1,2,3,4 1,2,3,5 1,3 1,3 1,3 3 1,3 1,3 1,3 1,3,6,7 1,3,6,8 NOTES: 1. All numbers shown are ideal, integer multiples of the CLK_MEM period. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. Includes signals MA[25:0], nPREG, and nPSKTSEL. 3. CMD refers to signals nPWE, nPOE, nPIOW, and nPIOR 4. Refer to the Intel(R) PXA27x Processor Family Developer's Manual, Expansion Memory Timing Configuration registers to change the assertion of CMD using the MCx[SET] bit fields. 5. Refer to the Intel(R) PXA27x Processor Family Developer's Manual, Expansion Memory Timing Configuration registers to increase the assertion of CMD using the MCx[HOLD] bit fields. 6. Refer to the Intel(R) PXA27x Processor Family Developer's Manual, Expansion Memory Timing Configuration registers to increase timings. The timings are changed by programming the MCx[ASST] respective bit fields. Refer to the PC Card Interface Command Assertion Code table to see the effect of MCx[ASST]. 7. tcdCLPS equals CLK_MEM * x_ASST_WAIT. Refer to the PC Card Interface Command Assertion Code table in the Intel(R) PXA27x Processor Family Developer's Manual for the correlation between x_ASST_WAIT and the MCx[ASST] bit field. 8. tcdPHCH equals CLK_MEM * x_ASST_HOLD. Refer to the PC Card Interface Command Assertion Code table in the Intel(R) PXA27x Processor Family Developer's Manual for the correlation between x_ASST_HOLD and the MCx[ASST] bit field. 6-40 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Figure 6-26. Expansion-Card Memory or I/O 16-Bit Access Timing Read Data Latch CLK_MEM nPCE[2],nPCE[1] tcdCHAI MA[25:0],nPREG,PSKTSEL tcdCLPS tcdPHCH tcdAVCL nPWE,nPOE,nPIOW,nPIOR tcdILCL nIOIS16 tcdDVCL MD[15:0] (write) RDnWR nPWAIT tcdDVCH tcdCHRDI MD[15:0] (read) tcdCHWDI tcdCHIH tcdCMD Electrical, Mechanical, and Thermal Specification 6-41 Intel(R) PXA270 Processor AC Timing Specifications Figure 6-27. Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing Read Data Latch CLK_MEM MA<25:1>,nPREG,PSKTSEL MA<0> nPCE<2> nPCE<1> tcdAVCL tcdCMD tcdCHAI nPIOW (or) nPIOR RDnWR tcdILCL nIOIS16 tcdPHCH tcdCLPS nPWAIT tcdDVCH tcdCHRDI MD<7:0> (read) tcdCHWDI MD<7:0> (write) tcdDVCL Low Byte tcdCHWDI High Byte tcdDVCH tcdCHRDI tcdCLPS tcdPHCH tcdCHIH tcdAVCL tcdCMD tcdCHAI Read Data Latch 6-42 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications 6.5 LCD Timing Specifications Figure 6-28 describes the LCD timing parameters. The LCD pin timing specifications are referenced to the pixel clock (L_PCLK_WR). Table 6-22 gives the values for the parameters. Figure 6-28. LCD Timing Definitions L_PCLK_WR Tpclkdv L_LDD[17:0] (rise) Tpclkdv L_LDD[17:0] (fall) L_LCLK_A0 L_BIAS Tpclklv Tpclkbv L_FCLK_RD Tpclkfv Table 6-22. LCD Timing Specifications Symbol Tpclkdv Tpclklv Tpclkfv Tpclkbv Description L_PCLK_WR rise/fall to L_LDD<17:0> driven valid L_PCLK_WR fall to L_LCLK_A0 driven valid L_PCLK_WR fall to L_FCLK_RD driven valid L_PCLK_WR rise to L_BIAS driven valid Min -- -- -- -- Max 14 14 14 14 Units ns ns ns ns Notes 1 2 2 2 NOTES: 1. The LCD data pins can be programmed to be driven on either the rising or falling edge of the pixel clock (L_PCLK_WR). 2. These LCD signals can toggle when L_PCLK_WR is not clocking (between frames). At this time, they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK_WR pin. Electrical, Mechanical, and Thermal Specification 6-43 Intel(R) PXA270 Processor AC Timing Specifications 6.6 SSP Timing Specifications Figure 6-29 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SSPCLK. Table 6-23 gives the values for the parameters. Note: In Figure 6-29, read the term "tSFMV" as "TSTXV." Figure 6-29. SSP Master Mode Timing Definitions SSPSCLK Tsfmv SSPSFRM Tsfmv SSPTXD Trxds Trxdh SSPRXD Table 6-23. SSP Master Mode Timing Specifications Symbol Tsfmv Trxds Trxdh Tsfmv Description SSPSCLK rise to SSPSFRM driven valid SSPRXD valid to SSPSCLK fall (input setup) SSPSCLK fall to SSPRXD invalid (input hold) SSPSCLK rise to SSPTXD valid Min Max 21 Units ns ns ns Notes 11 0 22 ns Figure 6-30. Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral PXA27x processor transmitting data PXA27x SSP (Slave Mode) transmitting data to external peripheral SSPSCLK (from Peripheral) tSCLK2TXD_output_delay SSPSFRM (from Peripheral) tSFRM2TXD_output_delay SSPTXD (from SSP) 6-44 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor AC Timing Specifications Table 6-24. Timing Specification SSP Slave Mode Transmitting Data to External Peripheral Parameter tSFRM2TXD_output_delay tSCLK2TXD_output_delay Description Frame to TX Data Out Clock to Tx Data Out Min Typ 10.58 10.52 Max Units ns ns Figure 6-31. Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral PXA27 processor receiving data PXA27x SSP (Slave Mode receiving data from external peripheral tSCLK_input_delay SSPSCLK (from Peripheral) SSPSFRM (from Peripheral) Data Capture tSFRM_input_delay SSPRXD (from Peripheral) tRXD_input_delay Data Capture Table 6-25. Timing Specification for SSP Slave Mode Receiving Data from External Peripheral Parameter tSFRM_input_delay tSCLK_input_delay tRXD_input_delay Description Frame to Rx Data Capture Clock to Rx Data Capture Rx Data Setup to Capture Min Typical 5.21 5.04 4.81 Max Units ns ns ns 6.7 JTAG Boundary Scan Timing Specifications Table 6-26 shows the AC specifications for the JTAG boundary-scan test signals. Figure 6-32 shows the timing diagram. Table 6-26. Boundary Scan Timing Specifications (Sheet 1 of 2) Symbol TBSF TBSCH TBSCL TBSCR TBSCF Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Min 0.0 15.0 15.0 -- -- Max 33.33 -- -- 5.0 5.0 Units MHz ns ns ns ns -- Notes Measured at 1.5 V Measured at 1.5 V 0.8 V to 2.0 V 2.0 V to 0.8 V Electrical, Mechanical, and Thermal Specification 6-45 Intel(R) PXA270 Processor AC Timing Specifications Table 6-26. Boundary Scan Timing Specifications (Sheet 2 of 2) Symbol TBSIS1 TBSIH1 TBSIS2 TBSIH2 TnTRST TBSOV1 TOF1 Parameter Input Setup to TCK TDI, TMS Input Hold from TCK TDI, TMS Input Setup to TCK nTRST Input Hold from TCK nTRST Assertion time of nTRST TDO Valid Delay TDO Float Delay Min 4.0 6.0 25.0 3.0 6 1.5 1.1 Max -- -- -- -- -- 6.9 5.4 Units ns ns ns ns ms ns ns -- -- -- -- -- Notes Relative to falling edge of TCK Relative to falling edge of TCK Figure 6-32. JTAG Boundary-Scan Timing TBSF TBSCH TBSCL TCK TBSIS2 nTRST TBSIS1 TBSIH1 TMS TBSIS1 TBSIH1 TDI TBSOV1 TBSOV1 TBSOV1 TBSOV1 TOF1 TBSOV1 TBSOV1 TBSOV1 TDO Controller State st -L og ic R -R un es Se -T et e le ct s t / I -D d Se R le le -Sc ct - IR a n -S ca C ap n tu re -IR TBSIH2 TnTRST Shift-IR it1 pd -IR at eIR Ex Run-Test/Idle -L og ic -R Te st es e t Te 6-46 Electrical, Mechanical, and Thermal Specification U Glossary 3G: An industry term used to describe the next, still-to-come generation of wireless applications. It represents a move from circuit-switched communications (where a device user has to dial in to a network) to broadband, high-speed, packet-based wireless networks (which are always on). The first generation of wireless communications relied on analog technology, followed by digital wireless communications. The third generation expands the digital capabilities by including high-speed connections and increased reliability. 802.11: Wireless specifications developed by the IEEE, outlining the means to manage packet traffic over a network and ensure that packets do not collide, which could result in the loss of data, when travelling from device to device. 8PSK: 8 phase shift key modulation scheme. Used in the EDGE standard. AC '97 AC-link standard serial interface for modem and audio ACK: Handshake packet indicating a positive acknowledgment. Active device: A device that is powered and is not in the suspended state. Air interface: the RF interface between a mobile cellular handset and the base station AMPS: Advanced Mobile Phone Service. A term used for analog technologies, the first generation of wireless technologies. Analog: Radio signals that are converted into a format that allows them to carry data. Cellular phones and other wireless devices use analog in geographic areas with insufficient digital networks. ARM* V5te: An ARM* architecture designation indicating the processor is conforms to ARM* architecture version 5, including "Thumb" mode and the "El Segundo" DSP extensions. Asynchronous Data: Data transferred at irregular intervals with relaxed latency requirements. Asynchronous RA: The incoming data rate, Fs i, and the outgoing data rate, Fs o, of the RA process are independent (i.e., there is no shared master clock). See also rate adaptation. Asynchronous SRC: The incoming sample rate, Fsi, and outgoing sample rate, Fso, of the SRC process are independent (i.e., there is no shared master clock). See also sample rate conversion. Audio device: A device that sources or sinks sampled analog data. AWG#: The measurement of a wire's cross-section, as defined by the American Wire Gauge standard. Babble: Unexpected bus activity that persists beyond a specified point in a (micro)frame. Backlight Inverter: A device to drive cold cathode fluorescent lamps used to illuminate LCD panels. Bandwidth: The amount of data transmitted per unit of time, typically bits per second (b/s) or bytes per second (B/s). The size of a network "pipe" or channel for communications in wired networks. In wireless, it refers to the range of available frequencies that carry a signal. Base Station:The telephone company's interface to the Mobile Station Electrical, Mechanical, and Thermal Specification Glossary-1 Intel(R) PXA270 Processor Glossary BGA: Ball Grid Array BFSK: binary frequency shift keying. A coding scheme for digital data. Bit: A unit of information used by digital computers. Represents the smallest piece of addressable memory within a computer. A bit expresses the choice between two possibilities and is typically represented by a logical one (1) or zero (0). Bit Stuffing: Insertion of a "0" bit into a data stream to cause an electrical transition on the data wires, allowing a PLL to remain locked. Blackberry: A two-way wireless device (pager) made by Research In Motion (RIM) that allows users to check e-mail and voice mail translated into text, as well as page other users of a wireless network service. It has a miniature "qwerty" keyboard that can be used by your thumbs, and uses SMS protocol. A Blackberry user must subscribe to the proprietary wireless service that allows for data transmission. Bluetooth: A short-range wireless specification that allows for radio connections between devices within a 30-foot range of each other. The name comes from 10th-century Danish King Harald Blatand (Bluetooth), who unified Denmark and Norway. BPSK: binary phase shift keying. A means of encoding digital data into a signal using phase-modulated communications. b/s: Transmission rate expressed in bits per second. B/s: Transmission rate expressed in bytes per second. BTB: Branch Target Buffer BTS: Base Transmitter Station Buffer: Storage used to compensate for a difference in data rates or time of occurrence of events, when transmitting data from one device to another. Bulk Transfer: One of the four USB transfer types. Bulk transfers are non-periodic, large bursty communication typically used for a transfer that can use any available bandwidth and can also be delayed until bandwidth is available. See also transfer type. Bus Enumeration: Detecting and identifying USB devices. Byte: A data element that is eight bits in size. Capabilities: Those attributes of a USB device that are administrated by the host. CAS: Cycle Accurate Simulator CAS-B4-RAS: See CBR. CBR: CAS Before RAS. Column Address Strobe Before Row Address Strobe. A fast refresh technique in which the DRAM keeps track of the next row it needs to refresh, thus simplifying what a system would have to do to refresh the part. CDMA: Code Division Multiple Access U.S. wireless carriers Sprint PCD and Verizon use CDMA to allocate bandwidth for users of digital wireless devices. CDMA distinguishes between multiple transmissions carried simultaneously on a single wireless signal. It carries the transmissions on that signal, freeing network room for the Glossary-2 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Glossary wireless carrier and providing interference-free calls for the user. Several versions of the standard are still under development. CDMA should increase network capacity for wireless carriers and improve the quality of wireless messaging. CDMA is an alternative to GSM. CDPD: Cellular Digital Packet Data Telecommunications companies can use DCPD to transfer data on unused cellular networks to other users. IF one section, or "cell" of the network is overtaxed, DCPD automatically allows for the reallocation of services. Cellular: Technology that senses analog or digital transmissions from transmitters that have areas of coverage called cells. As a user of a cellular phone moves between transmitters from one cell to another, the users' call travels from transmitter to transmitter uninterrupted. Circuit Switched: Used by wireless carriers, this method lets a user connect to a network or the Internet by dialing in, such as with a traditional phone line. Circuit switched connections are typically slower and less reliable than packet-switched networks, but are currently the primary method of network access for wireless users in the U.S. CF: Compact Flash memory and I/O card interface Characteristics: Those qualities of a USB device that are unchangeable; for example, the device class is a device characteristic. Client: Software resident on the host that interacts with the USB System Software to arrange data transfer between a function and the host. The client is often the data provider and consumer for transferred data. CML: Current mode logic Configuring Software: Software resident on the host software that is responsible for configuring a USB device. This may be a system configuration or software specific to the device. Control Endpoint: A pair of device endpoints with the same endpoint number that are used by a control pipe. Control endpoints transfer data in both directions and, therefore, use both endpoint directions of a device address and endpoint number combination. Thus, each control endpoint consumes two endpoint addresses. Control Pipe: Same as a message pipe. Control Transfer: One of the four USB transfer types. Control transfers support configuration/command/status type communications between client and function. See also transfer type. CRC: See Cyclic Redundancy Check. CSP: Chip Scale Package. CTE: Coefficient of thermal expansion CTI: Computer Telephony Integration. Cyclic Redundancy Check (CRC): A check performed on data to see if an error has occurred in transmitting, reading, or writing the data. The result of a CRC is typically stored or transmitted with the checked data. The stored or transmitted result is compared to a CRC calculated for the data to determine if an error has occurred. D-cache: Data cache DECT: the Digital European Cordless Telecommunications standard Default Address: An address defined by the USB Specification and used by a USB device when it is first powered or reset. The default address is 00H. Electrical, Mechanical, and Thermal Specification Glossary-3 Intel(R) PXA270 Processor Glossary Default Pipe: The message pipe created by the USB System Software to pass control and status information between the host and a USB device's endpoint zero. Device: A logical or physical entity that performs a function. The actual entity described depends on the context of the reference. At the lowest level, "device" may refer to a single hardware component, as in a memory device. At a higher level, it may refer to a collection of hardware components that perform a particular function, such as a USB interface device. At an even higher level, device may refer to the function performed by an entity attached to the USB; for example, a data/FAX modem device. Devices may be physical, electrical, addressable, and logical. When used as a non-specific reference, a USB device is either a hub or a function. Device Address: A seven-bit value representing the address of a device on the USB. The device address is the default address (00H) when the USB device is first powered or the device is reset. Devices are assigned a unique device address by the USB System Software. Device Endpoint: A uniquely addressable portion of a USB device that is the source or sink of information in a communication flow between the host and device. See also endpoint address. Device Resources: Resources provided by USB devices, such as buffer space and endpoints. See also Host Resources and Universal Serial Bus Resources. Device Software: Software that is responsible for using a USB device. This software may or may not also be responsible for configuring the device for use. DMA: Direct Memory Access Downstream: The direction of data flow from the host or away from the host. A downstream port is the port on a hub electrically farthest from the host that generates downstream data traffic from the hub. Downstream ports receive upstream data traffic. DQPSK: Differential Quadrature Phase Shift Keying a modulation technique used in TDMA. Driver: When referring to hardware, an I/O pad that drives an external load. When referring to software, a program responsible for interfacing to a hardware device, that is, a device driver. DSP: Digital Signal Processing DSTN Passive LCD Panel. Dual band mobile phone: A phone that supports both analog and digital technologies by picking up analog signals when digital signals fade. Most mobile phones are not dual-band. DWORD: Double word. A data element that is two words (i.e., four bytes or 32 bits) in size. Dynamic Insertion and Removal: The ability to attach and remove devices while the host is in operation. E2PROM: See Electrically Erasable Programmable Read Only Memory. EAV: End of active video EDGE: Enhanced Data GSM Environment. A faster version of the GSM standard. It is faster because it can carry messages using broadband networks that employ more bandwidth than standard GSM networks. EEPROM: See Electrically Erasable Programmable Read Only Memory. Electrically Erasable Programmable Read Only Memory (EEPROM): Non-volatile re-writable memory storage technology. Glossary-4 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Glossary End User: The user of a host. Endpoint: See device endpoint. Endpoint Address: The combination of an endpoint number and an endpoint direction on a USB device. Each endpoint address supports data transfer in one direction. Endpoint Direction: The direction of data transfer on the USB. The direction can be either IN or OUT. IN refers to transfers to the host; OUT refers to transfers from the host. Endpoint Number: A four-bit value between 0H and FH, inclusive, associated with an endpoint on a USB device. Envelope detector: An electronic circuit inside a USB device that monitors the USB data lines and detects certain voltage related signal characteristics. EOF: End-of-(micro)Frame. EOP: End-of-Packet. EOTD: Enhanced Observed Time Difference ETM: Embedded Trace Macrocell, the ARM* real-time trace capability External Port: See port. Eye pattern: A representation of USB signaling that provides minimum and maximum voltage levels as well as signal jitter. FAR: Fault Address Register, part of the ARM* architecture. False EOP: A spurious, usually noise-induced event that is interpreted by a packet receiver as an EOP. FDD: The Mobile Station transmits on one frequency; the Base Station transmits on another frequency FDM: Frequency Division Multiplexing. Each Mobile station transmits on a different frequency (within a cell). FDMA: Frequency Division Multiple Access. An analog standard that lets multiple users access a group of radio frequency bands and eliminates interference of message traffic. FHSS: See Frequency Hopping Spread Spectrum. FIQ: Fast Interrupt Request. See Interrupt Request. Frame: A 1 millisecond time base established on full-/low-speed buses. Frame Pattern: A sequence of frames that exhibit a repeating pattern in the number of samples transmitted per frame. For a 44.1 kHz audio transfer, the frame pattern could be nine frames containing 44 samples followed by one frame containing 45 samples. Frequency Hopping Spread Spectrum: A method by which a carrier spreads out packets of information (voice or data) over different frequencies. For example, a phone call is carried on several different frequencies so that when one frequency is lost another picks up the call without breaking the connection. Fs: See sample rate. FSR: Fault Status Register, part of the ARM* architecture. Electrical, Mechanical, and Thermal Specification Glossary-5 Intel(R) PXA270 Processor Glossary Full-duplex: Computer data transmission occurring in both directions simultaneously. Full-speed: USB operation at 12 Mb/s. See also low-speed and high-speed. Function: A USB device that provides a capability to the host, such as an ISDN connection, a digital microphone, or speakers. GMSK: Gaussian Minimum Shift Keying. A modulation scheme used in GSM. GPRS: General Packet Radio Service A technology that sends packets of data across a wireless network at speeds up to 114 Kbps. Unlike circuit-switched networks, wireless users do not have to dial in to networks to download information; GPRS wireless devices are "always on" in that they can send and receive data without dial-ins. GPRS works with GSM. GPS: Global Positioning Systems GSM: Global System for Mobile Communications. A standard for how data is coded and transferred through the wireless spectrum. The European wireless standard, also used in parts of Asia, GSM is an alternative to CDMA. GSM digitizes and compresses data and sends it across a channel with two other streams of user data. GSM is based on TDMA technology. Hamming Distance: The distance (number of bits) between encoded values that can change without causing a decode into the wrong value. Handshake Packet: A packet that acknowledges or rejects a specific condition. For examples, see ACK and NAK. HDML: Handheld Device Markup Language. HDML uses hypertext transfer protocol (HTTP) to display text versions of web pages on wireless devices. Unlike WML, HDML is not based on XML. HDML does not allow scripts, while WML uses a variant of JavaScript. Web site developers using HDML must re-code their web pages in HDML to be viewed on the smaller screen sizes of handheld devices. HARP: Windows CE standard development platform spec (Hardware Adaptation Reference Platform) High-bandwidth endpoint: A high-speed device endpoint that transfers more than 1024 bytes and less than 3073 bytes per microframe. High-speed: USB operation at 480 Mb/s. See also low-speed and full-speed. Host :The host computer system where the USB Host controller is installed. This includes the host hardware platform (CPU, bus, and so forth.) and the operating system in use. Host Controller: The host's USB interface. Host Controller Driver (HCD): The USB software layer that abstracts the Host controller hardware. The Host controller driver provides an SPI for interaction with a Host controller. The Host controller driver hides the specifics of the Host controller hardware implementation. Host Resources: Resources provided by the host, such as buffer space and interrupts. See also Device Resources and Universal Serial Bus Resources. HSTL: High-speed transceiver logic Hub: A USB device that provides additional connections to the USB. Hub Tier: One plus the number of USB links in a communication path between the host and a function. Glossary-6 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Glossary IMMU: Instruction Memory Management Unit, part of the Intel XScale(R) core. I-Mode: A Japanese wireless service for transferring packet-based data to handheld devices created by NTT DoCoMo. I-Mode is based on a compact version of HTML and does not currently use WAP. I-cache: Instruction cache IBIS: I/O Buffer Information Specification is a behavioral description of the I/O buffers and package characteristics of a semiconductor device. IBIS models use a standard format to make it easier to import data into circuit simulation software packages. iDEN: Integrated Digital Enhanced Network. A technology that allows users to access phone calls, two-way radio transmissions, paging and data transmissions from one wireless device. iDEN was developed by Motorola and based on TDMA. Interrupt Request (IRQ): A hardware signal that allows a device to request attention from a host. The host typically invokes an interrupt service routine to handle the condition that caused the request. Interrupt Transfer: One of the four USB transfer types. Interrupt transfer characteristics are small data, non-periodic, low-frequency, and bounded-latency. Interrupt transfers are typically used to handle service needs. See also transfer type. I/O Request Packet: An identifiable request by a software client to move data between itself (on the host) and an endpoint of a device in an appropriate direction. IrDA: Infrared Development Association IRP: See I/O Request Packet. IRQ: See Interrupt Request. ISI: Inter-signal interference. Data ghosting caused when multi-path delay causes previous symbols to interfere with the one currently being processed. ISM: Industrial, Scientific, and Medical band. Part of the wireless spectrum that is less regulated, such as 802.11. Isochronous Data: A stream of data whose timing is implied by its delivery rate. Isochronous Device: An entity with isochronous endpoints, as defined in the USB Specification, that sources or sinks sampled analog streams or synchronous data streams. Isochronous Sink Endpoint : An endpoint that is capable of consuming an isochronous data stream that is sent by the host. Isochronous Source Endpoint: An endpoint that is capable of producing an isochronous data stream and sending it to the host. Isochronous Transfer: One of the four USB transfer types. Isochronous transfers are used when working with isochronous data. Isochronous transfers provide periodic, continuous communication between host and device. See also transfer type. Jitter: A tendency toward lack of synchronization caused by mechanical or electrical changes. More specifically, the phase shift of digital pulses over a transmission medium. kb/s: Transmission rate expressed in kilobits per second. A measurement of bandwidth in the U.S. Electrical, Mechanical, and Thermal Specification Glossary-7 Intel(R) PXA270 Processor Glossary kB/s: Transmission rate expressed in kilobytes per second. Little endian: Method of storing data that places the least significant byte of multiple-byte values at lower storage addresses. For example, a 16-bit integer stored in little endian format places the least significant byte at the lower address and the most significant byte at the next address. LOA: Loss of bus activity characterized by an SOP without a corresponding EOP. Low-speed: USB operation at 1.5 Mb/s. See also full-speed and high-speed. LSb: Least significant bit. LSB: Least significant byte. LVDS: Low-voltage differential signal MAC: Multiply Accumulate unit Mb/s: Transmission rate expressed in megabits per second. MB/s: Transmission rate expressed in megabytes per second. MC: Media Center. A combination digital set-top box, video and music jukebox, personal video recorder and an Internet gateway and firewall that hooks up to a broadband connection. Message Pipe: A bidirectional pipe that transfers data using a request/data/status paradigm. The data has an imposed structure that allows requests to be reliably identified and communicated. Microframe: A 125 microsecond time base established on high-speed buses. MMC: Multimedia Card - small form factor memory and I/O card MMX Technology: The Intel(R) MMXTM technology comprises a set of instructions that are designed to greatly enhance the performance of advanced media and communications applications. See chapter 10 of the Intel(R) Architecture Software Developers Manual, Volume 3: System Programming Guide, Order #245472. Mobile Station: Cellular Telephone handset M-PSK: multilevel phase shift keying. A convention for encoding digital data in which there are multiple states. MMU: Memory Management Unit, part of the Intel XScale(R) core. MSb: Most significant bit. MSB: Most significant byte. MSL: Mobile Scalable Link. NAK: Handshake packet indicating a negative acknowledgment. Non Return to Zero Invert (NRZI): A method of encoding serial data in which ones and zeroes are represented by opposite and alternating high and low voltages where there is no return to zero (reference) voltage between encoded bits. Eliminates the need for clock pulses. NRZI: See Non Return to Zero Invert. Object: Host software or data structure representing a USB entity. Glossary-8 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Glossary OFDM: See Orthogonal Frequency Division Multiplexing. Orthogonal Frequency Division Multiplexing: A special form of multi-carrier modulation. In a multi-path channel, most conventional modulation techniques are sensitive to inter-symbol interference unless the channel symbol rate is small compared to the delay spread of the channel. OFDM is significantly less sensitive to inter-symbol interference, because a special set of signals is used to build the composite transmitted signal. The basic idea is that each bit occupies a frequency-time window that ensures little or no distortion of the waveform. In practice, it means that bits are transmitted in parallel over a number of frequency-nonselective channels. Packet: A bundle of data organized in a group for transmission. Packets typically contain three elements: control information (for example, source, destination, and length), the data to be transferred, and error detection and correction bits. Packet data is the basis for packet-switched networks, which eliminate the need to dial-in to send or receive information, because they are "always on." Packet Buffer: The logical buffer used by a USB device for sending or receiving a single packet. This determines the maximum packet size the device can send or receive. Packet ID (PID): A field in a USB packet that indicates the type of packet, and by inference, the format of the packet and the type of error detection applied to the packet. Packet Switched Network: Networks that transfer packets of data. PCMCIA: Personal Computer Memory Card Interface Association (PC Card) PCS: Personal Communications services. An alternative to cellular, PCD works like cellular technology because it sends calls from transmitter to transmitter as a caller moves. But PCS uses its own network, not a cellular network, and offers fewer "blind spots" than cellular, where calls are not available. PCS transmitters are generally closer together than their cellular counterparts. PDA: Personal Digital Assistant. A mobile handheld device that gives users access to text-based information. Users can synchronize their PDAs with a PC or network; some models support wireless communication to retrieve and send e-mail and get information from the Internet. Phase: A token, data, or handshake packet. A transaction has three phases. Phase Locked Loop (PLL): A circuit that acts as a phase detector to keep an oscillator in phase with an incoming frequency. Physical Device: A device that has a physical implementation; for example, speakers, microphones, and CD players. PID: See Packet ID or Process ID. PIO: Programmed input/output Pipe: A logical abstraction representing the association between an endpoint on a device and software on the host. A pipe has several attributes; for example, a pipe may transfer data as streams (stream pipe) or messages (message pipe). See also stream pipe and message pipe. PLL: See Phase Locked Loop. PM: Phase Modulation. Polling: Asking multiple devices, one at a time, if they have any data to transmit. POR: See Power On Reset. Electrical, Mechanical, and Thermal Specification Glossary-9 Intel(R) PXA270 Processor Glossary Port: Point of access to or from a system or circuit. For the USB, the point where a USB device is attached. Power On Reset (POR): Restoring a storage device, register, or memory to a predetermined state when power is applied. Process ID: Process identifier Programmable Data Rate: Either a fixed data rate (single-frequency endpoints), a limited number of data rates (32 kHz, 44.1 kHz, 48 kHz, ...), or a continuously programmable data rate. The exact programming capabilities of an endpoint must be reported in the appropriate class-specific endpoint descriptors. Protocol: A specific set of rules, procedures, or conventions relating to format and timing of data transmission between two devices. PSP: Programmable Serial Protocol PWM: Pulse Width Modulator QBS: Qualification By Similarity. A technique allowed by JEDEC for part qualification when target parameters are fully understood and data exist to warrant omitting a specific test. QAM: quadrature amplitude modulation. A coding scheme for digital data. QPSK: quadrature phase shift keying. A convention for encoding digital data into a signal using phase-modulated communications. RA: See rate adaptation. Radio Frequency Device: These devices use radio frequencies to transmit data. One typical use is for bar code scanning of products in a warehouse or distribution center, and sending that information to an ERP database. Rate Adaptation: The process by which an incoming data stream, sampled at Fs i, is converted to an outgoing data stream, sampled at Fs o, with a certain loss of quality, determined by the rate adaptation algorithm. Error control mechanisms are required for the process. Fs i and Fs o can be different and asynchronous. Fs i is the input data rate of the RA; Fs o is the output data rate of the RA. Request: A request made to a USB device contained within the data portion of a SETUP packet. Retire: The action of completing service for a transfer and notifying the appropriate software client of the completion. RGBT: Red, Green, Blue, Transparency ROM: Read Only Memory. Root Hub: A USB hub directly attached to the Host controller. This hub (tier 1) is attached to the host. Root Port: The downstream port on a Root Hub. RTC: Real-Time Clock SA-1110: StrongARM* based applications processor for handheld products Intel(R) StrongARM* SA-1111: Companion chip for the Intel(R) SA-1110 processor SAD: Sum of absolute differences Glossary-10 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Glossary Sample: The smallest unit of data on which an endpoint operates; a property of an endpoint. Sample Rate (Fs): The number of samples per second, expressed in Hertz (Hz). Sample Rate Conversion (SRC): A dedicated implementation of the RA process for use on sampled analog data streams. The error control mechanism is replaced by interpolating techniques. Service A procedure provided by a System Programming Interface (SPI). Satellite Phone: Phones that connect callers by satellite. Users have a world-wide alternative to terrestrial connections. Typical use is for isolated users, such as crews of deep-see oil rigs with phones configured to connect to a satellite service. SAV: Start of active video SAW: Surface Acoustic Wave filter SDRAM: Synchronous Dynamic Random Access Memory. Service Interval: The period between consecutive requests to a USB endpoint to send or receive data. Service Jitter: The deviation of service delivery from its scheduled delivery time. Service Rate: The number of services to a given endpoint per unit time. SIMD: Single Instruction Multiple Data (a parallel processing architecture). Smart Phone: A combination of a mobile phone and a PDA, which allow users to communicate as well as perform tasks; such as, accessing the Internet and storing contacts in a database. Smart phones have a PDA-like screen. SMROM: Synchronous Mask ROM SMS: Short Messaging Service. A service through which users can send text-based messages from one device to another. The message can be up to 160 characters and appears on the screen of the receiving device. SMS works with GSM networks. SOC: System On Chip SOF: See Start-of-Frame. SOP: Start-of-Packet. SPI: See System Programming Interface. Also, "Serial Peripheral Interface protocol. SPI: Serial Peripheral Interface Split transaction: A transaction type supported by host controllers and hubs. This transaction type allows full- and low-speed devices to be attached to hubs operating at high-speed. Spread Spectrum: An encoding technique patented by actress Hedy Lamarr and composer George Antheil, which broadcasts a signal over a range of frequencies. SRAM: Static Random Access Memory. SRC: See Sample Rate Conversion. SSE: Streaming SIMD Extensions Electrical, Mechanical, and Thermal Specification Glossary-11 Intel(R) PXA270 Processor Glossary SSE2: Streaming SIMD Extensions 2: for Intel Architecture machines, 144 new instructions, a 128-bit SIMD integer arithmetic and 128-bit SIMD double precision floating point instructions, enabling enhanced multimedia experiences. SSP: Synchronous Serial Port SSTL: Stub series terminated logic Stage: One part of the sequence composing a control transfer; stages include the Setup stage, the Data stage, and the Status stage. Start-of-Frame (SOF): The first transaction in each (micro)frame. An SOF allows endpoints to identify the start of the (micro)frame and synchronize internal endpoint clocks to the host. Stream Pipe: A pipe that transfers data as a stream of samples with no defined USB structure SWI: Software interrupt. Synchronization Type: A classification that characterizes an isochronous endpoint's capability to connect to other isochronous endpoints. Synchronous RA: The incoming data rate, Fsi, and the outgoing data rate, Fso, of the RA process are derived from the same master clock. There is a fixed relation between Fsi and Fso. Synchronous SRC: The incoming sample rate, Fsi, and outgoing sample rate, Fso, of the SRC process are derived from the same master clock. There is a fixed relation between Fsi and Fso. System Programming Interface (SPI): A defined interface to services provided by system software. TC: Temperature Cycling TDD: Time Division Duplexing The Mobile Station and the Base Station transmit on same frequency at different times. TDM: See Time Division Multiplexing. TDMA: Time Division Multiple Access. TDMA protocol allows multiple users to access a single radio frequency by allocating time slots for use to multiple voice or data calls. TDMA breaks down data transmissions, such as a phone conversation, into fragments and transmits each fragment in a short burst, assigning each fragment a time slot. With a cell phone, the caller would not detect this fragmentation. TDMA works with GSM and digital cellular services. TDR: See Time Domain Reflectometer. Termination: Passive components attached at the end of cables to prevent signals from being reflected or echoed. TFT: Thin Film Twist, a type of active LCD panel. Three-state: a high-impedance state in which the output is floating and is electrically isolated from the buffer's circuitry. Time Division Multiplexing (TDM): A method of transmitting multiple signals (data, voice, and/or video) simultaneously over one communications medium by interleaving a piece of each signal one after another. Time Domain Reflectometer (TDR): An instrument capable of measuring impedance characteristics of the USB signal lines. Glossary-12 Electrical, Mechanical, and Thermal Specification Intel(R) PXA270 Processor Glossary Time-out: The detection of a lack of bus activity for some predetermined interval. Token Packet: A type of packet that identifies what transaction is to be performed on the bus. TPV: Third Party Vendor Transaction: The delivery of service to an endpoint; consists of a token packet, optional data packet, and optional handshake packet. Specific packets are allowed/required based on the transaction type. Transaction translator: A functional component of a USB hub. The Transaction Translator responds to special high-speed transactions and translates them to full/low-speed transactions with full/low-speed devices attached on downstream facing ports. Transfer: One or more bus transactions to move information between a software client and its function. Transfer Type: Determines the characteristics of the data flow between a software client and its function. Four standard transfer types are defined: control, interrupt, bulk, and isochronous. TS: Thermal Shock Turn-around Time: The time a device needs to wait to begin transmitting a packet after a packet has been received to prevent collisions on the USB. This time is based on the length and propagation delay characteristics of the cable and the location of the transmitting device in relation to other devices on the USB. UART: Universal Asynchronous Receiver/Transmitter serial port Universal Serial Bus Driver (USBD): The host resident software entity responsible for providing common services to clients that are manipulating one or more functions on one or more Host controllers. Universal Serial Bus Resources: Resources provided by the USB, such as bandwidth and power. See also Device Resources and Host Resources. Upstream: The direction of data flow towards the host. An upstream port is the port on a device electrically closest to the host that generates upstream data traffic from the hub. Upstream ports receive downstream data traffic. USBD: See Universal Serial Bus Driver. USB-IF: USB Implementers Forum, Inc. is a nonprofit corporation formed to facilitate the development of USB compliant products and promote the technology. VBI: Vertical Blanking Interval, also known as the "backporch". Virtual Device: A device that is represented by a software interface layer. An example of a virtual device is a hard disk with its associated device driver and client software that makes it able to reproduce an audio.WAV file. VLIO: Variable Latency Input/Output interface. YUV: A method of characterizing video signals typically used in digital cameras and PAL television specifying luminance and chrominance. WAP: Wireless Application Protocol. WAP is a set of protocols that lets users of mobile phones and other digital wireless devices access Internet content, check voice mail and e-mail, receive text of faxes and conduct transactions. WAP works with multiple standards, including CDMA and GSM. Not all mobile devices support WAP. Electrical, Mechanical, and Thermal Specification Glossary-13 Intel(R) PXA270 Processor Glossary W-CDMA: Wideband CDMA, a third generation wireless technology under development that allows for high-speed, high-quality data transmission. Derived from CDMA, W-CDMA digitizes and transmits wireless data over a broad range of frequencies. It requires more bandwidth than CDMA, but offers faster transmission because it optimizes the use of multiple wireless signals, instead of one, as does CDMA. Wireless LAN: A wireless LAN uses radio frequency technology to transmit network messages through the air for relatively short distances, like across an office building or a college campus. A wireless LAN can serve as a replacement for, or an extension to, a traditional wired LAN. Wireless Spectrum: A band of frequencies where wireless signals travel carrying voice and data information. Word: A data element that is four bytes (32 bits) in size. WML: Wireless Markup Language, a version of HDML is based on XML. Wireless applications developers use WML to re-target content for wireless devices. Glossary-14 Electrical, Mechanical, and Thermal Specification |
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